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2020 – today
- 2024
[j30]Bahram Rashidi:
Efficient and low-cost approximate multipliers for image processing applications. Integr. 94: 102084 (2024)- [j29]Bahram Rashidi:
Fault-tolerant and error-correcting 4-bit S-boxes for cryptography applications with multiple errors detection. J. Supercomput. 80(2): 1464-1490 (2024) - [j28]Bahram Rashidi:
APPAs: fast and efficient approximate parallel prefix adders and multipliers. J. Supercomput. 80(16): 24269-24296 (2024) - 2023
- [j27]Bahram Rashidi
:
Error-correcting cryptographic S-boxes with multiple error detection and correction. Int. J. Circuit Theory Appl. 51(11): 5499-5511 (2023) - [j26]Bahram Rashidi:
Lightweight Cryptographic S-Boxes Based on Efficient Hardware Structures for Block Ciphers. ISC Int. J. Inf. Secur. 15(1): 137-151 (2023) - 2022
- [j25]Bahram Rashidi:
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter. Integr. 85: 20-26 (2022) - 2021
- [j24]Bahram Rashidi:
Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things. IET Comput. Digit. Tech. 15(3): 171-184 (2021) - [j23]Bahram Rashidi:
Lightweight 8-bit S-box and combined S-box/S-box-1 for cryptographic applications. Int. J. Circuit Theory Appl. 49(8): 2348-2362 (2021) - [j22]Bahram Rashidi:
Compact and efficient structure of 8-bit S-box for lightweight cryptography. Integr. 76: 172-182 (2021) - [j21]Bahram Rashidi:
Efficient full data-path width and serialized hardware structures of SPONGENT lightweight hash function. Microelectron. J. 115: 105167 (2021) - 2020
- [j20]Bahram Rashidi:
Flexible structures of lightweight block ciphers PRESENT, SIMON and LED. IET Circuits Devices Syst. 14(3): 369-380 (2020) - [j19]Bahram Rashidi:
Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher. IET Comput. Digit. Tech. 14(2): 69-79 (2020) - [j18]Bahram Rashidi:
Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher. Int. J. Circuit Theory Appl. 48(8): 1227-1243 (2020) - [j17]Bahram Rashidi:
Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication. J. Hardw. Syst. Secur. 4(2): 120-135 (2020)
2010 – 2019
- 2019
- [j16]Bahram Rashidi:
Efficient and high-throughput application-specific integrated circuit implementations of HIGHT and PRESENT block ciphers. IET Circuits Devices Syst. 13(6): 731-740 (2019) - [j15]Bahram Rashidi:
Efficient hardware structure for extended Euclidean-based inversion over F 2 m. IET Comput. Digit. Tech. 13(4): 282-291 (2019) - [j14]Bahram Rashidi:
High-throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers. Int. J. Circuit Theory Appl. 47(8): 1254-1268 (2019) - [j13]Bahram Rashidi, Mohammad Abedini:
Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems. J. Circuits Syst. Comput. 28(9): 1950149:1-1950149:30 (2019) - [j12]Bahram Rashidi:
High-throughput and lightweight hardware structures of HIGHT and PRESENT block ciphers. Microelectron. J. 90: 232-252 (2019) - 2018
- [j11]Bahram Rashidi:
Efficient hardware implementations of point multiplication for binary Edwards curves. Int. J. Circuit Theory Appl. 46(8): 1516-1533 (2018) - 2017
- [j10]Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems. IET Circuits Devices Syst. 11(2): 103-112 (2017) - [j9]Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
Full-custom hardware implementation of point multiplication on binary Edwards curves for application-specific integrated circuit elliptic curve cryptosystem applications. IET Circuits Devices Syst. 11(6): 568-578 (2017) - [j8]Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi:
High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2 m ). IET Inf. Secur. 11(2): 66-77 (2017) - [j7]Bahram Rashidi:
High-speed hardware implementation of Gaussian normal basis inversion algorithm over F2m. Microelectron. J. 63: 138-147 (2017) - [i4]Bahram Rashidi:
A Survey on Hardware Implementations of Elliptic Curve Cryptosystems. CoRR abs/1710.08336 (2017) - [i3]Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi:
High-speed Hardware Implementations of Point Multiplication for Binary Edwards and Generalized Hessian Curves. IACR Cryptol. ePrint Arch. 2017: 5 (2017) - 2016
- [j6]Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m ). IET Comput. Digit. Tech. 10(1): 18-29 (2016) - [j5]Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m). Integr. 55: 138-154 (2016) - [j4]Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems. Microelectron. J. 52: 49-65 (2016) - [i2]Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
High-speed VLSI implementation of Digit-serial Gaussian normal basis Multiplication over GF(2m). IACR Cryptol. ePrint Arch. 2016: 966 (2016) - 2015
- [j3]Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi:
Efficient implementation of low time complexity and pipelined bit-parallel polynomial basis multiplier over binary finite fields. ISC Int. J. Inf. Secur. 7(2): 101-114 (2015) - [i1]Bahram Rashidi, Sayed Masoud Sayedi, Reza Rezaeian Farashahi:
Efficient and Low-complexity Hardware Architecture of Gaussian Normal Basis Multiplication over GF(2m) for Elliptic Curve Cryptosystems. IACR Cryptol. ePrint Arch. 2015: 1109 (2015) - 2014
- [j2]Reza Rezaeian Farashahi, Bahram Rashidi, Sayed Masoud Sayedi:
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm. Microelectron. J. 45(8): 1014-1025 (2014) - [c1]Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi:
High-speed and pipelined finite field bit-parallel multiplier over GF(2m) for elliptic curve cryptosystems. ISCISC 2014: 15-20 - 2013
- [j1]Bahram Rashidi:
High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA. IET Signal Process. 7(8): 743-753 (2013)
Coauthor Index
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