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ORCIDEdgar-Andrei Vega-Ochoa
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2020 – today
- 2020
[j2]Francisco E. Rangel-Patino
, Andres Viveros-Wacher, José Ernesto Rayas-Sánchez, Ismael Duron-Rosales, Edgar-Andrei Vega-Ochoa, Nagib Hakim, Enrique Lopez-Miralrio:
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation. IEEE Trans. Emerg. Top. Comput. 8(2): 453-463 (2020)
2010 – 2019
- 2019
- [j1]Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Andres Viveros-Wacher, José Luis Chavez-Hurtado, Edgar-Andrei Vega-Ochoa, Nagib Hakim:
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 733-740 (2019) - 2018
- [c4]Andres Viveros-Wacher, Ricardo Baca-Baylon, Francisco E. Rangel-Patino, Miguel A. Davalos-Santana, Edgar-Andrei Vega-Ochoa, José Ernesto Rayas-Sánchez:
Jitter tolerance acceleration using the golden section optimization technique. LASCAS 2018: 1-4 - [c3]Francisco E. Rangel-Patino, José Ernesto Rayas-Sánchez, Edgar-Andrei Vega-Ochoa, Nagib Hakim:
Direct optimization of a PCI express link equalization in industrial post-silicon validation. LATS 2018: 1-6 - 2014
- [c2]Jesus-Andres Mendoza-Bonilla, Alejandro Cortez-Ibarra, Edgar-Andrei Vega-Ochoa, Francisco Rangel-Patino, Brandon Gore:
Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation. VLSI-SoC 2014: 1-6 - [c1]Andres Viveros-Wacher, Ricardo Alejos, Liliana Alvarez, Israel Diaz-Castro, Brenda Marcial, Gaston Motola-Acuna, Edgar-Andrei Vega-Ochoa:
SMV methodology enhancements for high speed I/O links of SoCs. VTS 2014: 1-5
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