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Jim Covino

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Journal Articles

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2003
[j2]
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  - journals/jssc/PiloABBCCL03
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  - https://dblp.org/rec/journals/jssc/PiloABBCCL03
Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier:
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38(11): 1974-1980 (2003)
2000
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Harold Pilo, Archie Allen, Jim Covino, Patrick Hansen, Steve Lamphier, Chris Murphy, Terry Traver, Pui Yee:
An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin. IEEE J. Solid State Circuits 35(11): 1641-1647 (2000)

Conference and Workshop Papers

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2007
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Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC 2007: 795-798

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