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Books and Theses
- 2014
[b1]Chuan Shan:
Distributed clock generator for globally and locally synchronous chips with a large size. (Générateur distribué d'horloge pour puces globalement et localement synchrones de grande taille). Pierre and Marie Curie University, Paris, France, 2014
Journal Articles
- 2019
- [j2]Dimitri Galayko
, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard:
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1673-1677 (2019) - 2013
- [j1]Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell:
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectron. J. 44(9): 840-843 (2013)
Conference and Workshop Papers
- 2016
- [c9]Eugene Koskin, Elena Blokhina, Chuan Shan, Eldar Zianbetov, Orla Feely, Dimitri Galayko:
Discrete-time modelling and experimental validation of an All-Digital PLL for clock-generating networks. NEWCAS 2016: 1-4 - 2015
- [c8]Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko:
A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs. NEWCAS 2015: 1-4 - 2014
- [c7]Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov:
"Swimming pool"-like distributed architecture for clock generation in large many-core SoC. ISCAS 2014: 2768-2771 - [c6]Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov:
A reconfigurable distributed architecture for clock generation in large many-core SoC. ReCoSoC 2014: 1-8 - 2013
- [c5]Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard:
Distributed clock generator for synchronous SoC using ADPLL network. CICC 2013: 1-4 - [c4]Chuan Shan, Dimitri Galayko, François Anceau:
On-chip clock error characterization for clock distribution system. ISVLSI 2013: 102-108 - [c3]Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko:
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation. ReConFig 2013: 1-6 - 2012
- [c2]Chuan Shan, Dimitri Galayko, François Anceau:
Design and Modeling of ADPLL with sliding-window for wide range frequency tracking. NEWCAS 2012: 269-272 - 2011
- [c1]Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard:
FPGA implementation of reconfigurable ADPLL network for distributed clock generation. FPT 2011: 1-4
Coauthor Index
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