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2020 – today
- 2020
[c6]Su-Hao Wu, Yun-Shiang Shu, Albert Yen-Chih Chiou, Wei-Hsiang Huang, Zhi-Xin Chen, Hung-Yi Hsieh:
9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s. ISSCC 2020: 154-156- [c5]Yun-Shiang Shu, Zhi-Xin Chen, Yu-Hong Lin, Su-Hao Wu, Wei-Hsiang Huang, Albert Yen-Chih Chiou, Chang-Yang Huang, Hung-Yi Hsieh, Fan-Wei Liao, Teng-Feng Zou, Ping Chen:
26.1 A 4.5mm2 Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices. ISSCC 2020: 400-402
2010 – 2019
- 2019
- [c4]Wei-Hsiang Huang, Su-Hao Wu, Zhi-Xin Chen, Yun-Shiang Shu:
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range. VLSI Circuits 2019: 70- - [c3]Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang:
A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS. VLSI Circuits 2019: 228- - 2016
- [c2]Su-Hao Wu, Tsung-Kai Kao, Zwei-Mei Lee, Ping Chen, Jui-Yuan Tsai:
15.6 A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique. ISSCC 2016: 280-281 - 2013
- [j1]Su-Hao Wu, Jieh-Tsorng Wu:
A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration. IEEE J. Solid State Circuits 48(9): 2170-2179 (2013) - [c1]Su-Hao Wu, Jieh-Tsorng Wu:
Background calibration of integrator leakage in discrete-time delta-sigma modulators. NEWCAS 2013: 1-4
Coauthor Index
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