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ORCIDHarijot Singh Bindra
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Journal Articles
- 2023
[j4]Yuting Shen
, Hanyue Li, Harijot Singh Bindra, Eugenio Cantatore, Pieter Harpe:
A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1719-1723 (2023)- 2022
- [j3]Maikel Huiskamp, Mark S. Oude Alink, Bram Nauta, Anne-Johan Annema, Harijot Singh Bindra:
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 999-1012 (2022) - 2021
- [j2]Joeri Lechevallier, Harijot Singh Bindra, Ronan A. R. van der Zee, Bram Nauta:
Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging. IEEE J. Solid State Circuits 56(8): 2427-2437 (2021) - 2018
- [j1]Harijot Singh Bindra, Chris E. Lokin, Daniël Schinkel, Anne-Johan Annema, Bram Nauta:
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise. IEEE J. Solid State Circuits 53(7): 1902-1912 (2018)
Conference and Workshop Papers
- 2022
- [c7]Harijot Singh Bindra, Jeroen Ponte, Bram Nauta:
A 174μVRMS Input Noise, 1 G8/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch. ISSCC 2022: 1-3 - 2019
- [c6]Harijot Singh Bindra, Anne-Johan Annema, Gerard Wienk, Bram Nauta, Simon M. Louwsma:
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. CICC 2019: 1-4 - [c5]Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta:
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits 2019: 74- - 2017
- [c4]Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta:
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC 2017: 217-220 - [c3]Harijot Singh Bindra, Chris E. Lokin, Anne-Johan Annema, Bram Nauta:
A 30fJ/comparison dynamic bias comparator. ESSCIRC 2017: 71-74 - [c2]Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta:
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC 2017: 235-238 - 2013
- [c1]Harijot Singh Bindra, Shouri Chatterjee, Kaushik Saha, Taranjit Kukal:
Clock and data recovery module in 90nm for 10Gbps serial link with -18dB channel attenuation. ISCAS 2013: 2472-2475
Coauthor Index
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