"A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and ..."

Harijot Singh Bindra et al. (2019)

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DOI: 10.23919/VLSIC.2019.8778093

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Bram Nauta:
A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. VLSI Circuits 2019: 74-

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