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ORCIDTravis Forbes
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2020 – today
- 2023
[j3]Travis Forbes
, Benjamin Magstadt, Jesse Moody, Justine Saugen, Andrew Suchanek, Spencer Nelson:
A 0.2-2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55-448.6 ns Programmable Delay Range and 330 ns/mm2 Area Efficiency. IEEE J. Solid State Circuits 58(8): 2349-2359 (2023)
2010 – 2019
- 2015
- [c5]Wei-Gi Ho, Travis Forbes, Ranjit Gharpurey:
A low-power two-stage harmonic rejection quadrature mixer employing bias-current reuse. MWSCAS 2015: 1-4 - 2014
- [j2]Travis Forbes, Ranjit Gharpurey:
A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver. IEEE J. Solid State Circuits 49(9): 1971-1983 (2014) - [c4]Vineet Kumar Singh, Travis Forbes, Wei-Gi Ho, Jaegan Ko, Ranjit Gharpurey:
A 16-band channelizer employing harmonic rejection mixers with enhanced image rejection. CICC 2014: 1-4 - 2013
- [j1]Travis Forbes, Wei-Gi Ho, Ranjit Gharpurey:
Design and Analysis of Harmonic Rejection Mixers With Programmable LO Frequency. IEEE J. Solid State Circuits 48(10): 2363-2374 (2013) - [c3]Travis Forbes, Wei-Gi Ho, Nan Sun, Ranjit Gharpurey:
A frequency-folded ADC architecture with digital LO synthesis. ISCAS 2013: 149-152 - [c2]Wei-Gi Ho, Travis Forbes, Vineet Kumar Singh, Ranjit Gharpurey:
An active interference cancellation technique with harmonic rejection for a broadband channelizer. MWSCAS 2013: 586-589 - 2012
- [c1]Travis Forbes, Ranjit Gharpurey:
Embedded LO synthesis method in harmonic rejection mixers. MWSCAS 2012: 750-753
Coauthor Index
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