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ORCIDShairfe Muhammad Salahuddin
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2020 – today
- 2024
[j3]Hsiao-Hsuan Liu
, Carlo Gilardi, Shairfe Muhammad Salahuddin, Zhenlin Pei, Pieter Schuddinck, Yang Xiang, Pieter Weckx, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert, Chenyun Pan, Subhasish Mitra, Francky Catthoor:
Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. IEEE Trans. Circuits Syst. I Regul. Pap. 71(12): 6495-6506 (2024)- 2023
- [j2]Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor:
3D SRAM Macro Design in 3D Nanofabric Process Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2858-2867 (2023) - [c6]Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan:
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access. ISQED 2023: 1 - 2022
- [c5]Alessio Spessot, Shairfe Muhammad Salahuddin, Ricardo Escobar, Romain Ritzenthaler, Yang Xiang, Rahul Budhwani, Eugenio Dentoni Litta, Elena Capogreco, Joao Bastos, Yangyin Chen, Naoto Horiguchi:
Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations. IMW 2022: 1-4
2010 – 2019
- 2016
- [j1]Shairfe Muhammad Salahuddin, Volkan Kursun:
Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability. J. Circuits Syst. Comput. 25(1): 1640009:1-1640009:19 (2016) - 2014
- [c4]Shairfe Muhammad Salahuddin, Volkan Kursun:
High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins. ISIC 2014: 312-315 - 2013
- [c3]Shairfe Muhammad Salahuddin, Volkan Kursun:
Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption. ICECS 2013: 25-28 - [c2]Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun:
Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability. ISCAS 2013: 2331-2334 - [c1]Shairfe Muhammad Salahuddin, Hailong Jiao, Volkan Kursun:
A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. ISQED 2013: 353-358
Coauthor Index
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