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ORCIDTobias Strauch
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2020 – today
- 2024
[c12]Tobias Strauch:
Deductive Formal Verification of Synthesizable, Transaction-Level Hardware Designs Using Coq. DATE 2024: 1-6- 2023
- [c11]Tobias Strauch
:
MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations for Object-oriented Model-driven Prototyping. RSP 2023: 06:1-06:7
2010 – 2019
- 2019
- [c10]Tobias Strauch:
An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- and Random-Access-Scan (RAS). DSD 2019: 51-60 - [c9]Tobias Strauch:
Combining Simulation and FPGA Based Verification to an Affordable and Ultra-Fast Multi-Billion-Gate Verification System. RSP 2019: 22-28 - 2018
- [c8]Tobias Strauch:
Dynamic Inside-Out Verification Using Inverse Transactions in TLM. FDL 2018: 5-16 - [i5]Tobias Strauch:
Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++. CoRR abs/1807.05442 (2018) - [i4]Tobias Strauch:
Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs. CoRR abs/1807.05446 (2018) - 2017
- [j3]Tobias Strauch:
Connecting Things to the IoT by Using Virtual Peripherals on a Dynamically Multithreaded Cortex M3. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2462-2469 (2017) - [c7]Tobias Strauch:
An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL). DSD 2017: 30-39 - [c6]Tobias Strauch:
Acceleration Techniques for System-Hyper-Pipelined Soft-Processors on FPGAs. DSD 2017: 119-128 - [c5]Tobias Strauch:
A Novel RTL ATPG Model Based on Gate Inherent Faults of Complex Gates. MBMV 2017: 117-128 - 2016
- [i3]Tobias Strauch:
A Novel RTL ATPG Model Based on Gate Inherent Faults (GIF-PO) of Complex Gates. CoRR abs/1612.05166 (2016) - 2015
- [c4]Tobias Strauch:
The Effects of System Hyper Pipelining on Three Computational Benchmarks Using FPGAs. ARC 2015: 280-290 - [c3]Tobias Strauch:
Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++. MBMV 2015: 173-182 - [i2]Tobias Strauch:
Running Identical Threads in C-Slow Retiming based Designs for Functional Failure Detection. CoRR abs/1502.01237 (2015) - [i1]Tobias Strauch:
Using System Hyper Pipelining (SHP) to Improve the Performance of a Coarse-Grained Reconfigurable Architecture (CGRA) Mapped on an FPGA. CoRR abs/1508.07139 (2015) - 2013
- [c2]Tobias Strauch:
Timing driven RTL-to-RTL partitioner for multi-FPGA systems. FPL 2013: 1-4 - [c1]Tobias Strauch:
Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs. PARCO 2013: 515-522 - 2012
- [j2]Tobias Strauch:
Single Cycle Access Structure for Logic Test. IEEE Trans. Very Large Scale Integr. Syst. 20(5): 878-891 (2012) - 2011
- [j1]Tobias Strauch:
Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing. IEEE Trans. Very Large Scale Integr. Syst. 19(9): 1549-1558 (2011)
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