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ORCIDHarald P. E. Vranken
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2010 – 2019
- 2019
[j8]Jens Haag, Harald P. E. Vranken, Marko C. J. D. van Eekelen:
A Virtual Classroom for Cybersecurity Education. Trans. Edutainment 15: 173-208 (2019)- [c30]Sanjay Kumar, Harald P. E. Vranken, Joost van Dijk, Timo Hämäläinen
:
Deep in the Dark: A Novel Threat Detection System using Darknet Traffic. IEEE BigData 2019: 4273-4279 - 2018
- [j7]Lars Kröhnke, Jelte Jansen, Harald P. E. Vranken:
Resilience of the Domain Name System: A case study of the .nl-domain. Comput. Networks 139: 136-150 (2018) - [j6]Sven Kiljan, Harald P. E. Vranken, Marko C. J. D. van Eekelen:
Evaluation of transaction authentication methods for online banking. Future Gener. Comput. Syst. 80: 430-447 (2018) - [c29]Jorrit Kronjee, Arjen Hommersom, Harald P. E. Vranken:
Discovering software vulnerabilities using data-flow analysis and machine learning. ARES 2018: 6:1-6:10 - [c28]Eef van Es, Harald P. E. Vranken, Arjen Hommersom:
Denial-of-Service Attacks on LoRaWAN. ARES 2018: 17:1-17:6 - [c27]Jos van Roosmalen, Harald P. E. Vranken, Marko C. J. D. van Eekelen:
Applying deep learning on packet flows for botnet detection. SAC 2018: 1629-1636 - 2017
- [j5]Sven Kiljan, Koen Simoens, Danny De Cock, Marko C. J. D. van Eekelen, Harald P. E. Vranken:
A Survey of Authentication and Communications Security in Online Banking. ACM Comput. Surv. 49(4): 61:1-61:35 (2017) - 2016
- [c26]Jeroen Pijpker, Harald P. E. Vranken:
The Role of Internet Service Providers in Botnet Mitigation. EISIC 2016: 24-31 - [c25]Sven Kiljan, Harald P. E. Vranken, Marko C. J. D. van Eekelen:
User-friendly Manual Transfer of Authenticated Online Banking Transaction Data - A Case Study that Applies the What You Enter Is What You Sign Transaction Authorization Information Scheme. SECRYPT 2016: 259-270 - 2014
- [c24]Jens Haag, Stefan Karsch, Harald P. E. Vranken, Marko C. J. D. van Eekelen:
An Exercise Assistant for Practical Networking and IT Security Courses in Higher Education. CSEDU (Selected Papers) 2014: 84-98 - [c23]Jens Haag, Christian Witte, Stefan Karsch, Harald P. E. Vranken, Marko C. J. D. van Eekelen:
An Exercise Assistant for Practical Networking Courses. CSEDU (1) 2014: 97-104 - [c22]Sven Kiljan, Harald P. E. Vranken, Marko C. J. D. van Eekelen:
What You Enter Is What You Sign: Input Integrity in an Online Banking Environment. STAST 2014: 40-47 - 2013
- [c21]Timo Schless, Harald P. E. Vranken:
Counter botnet activities in the Netherlands a study on organisation and effectiveness. ICITST 2013: 437-442 - 2011
- [c20]Jurriaan Kamer, Harald P. E. Vranken:
The Impact of Server Virtualization on ITIL Processes. CLOSER 2011: 643-649 - [c19]Harald P. E. Vranken, Jens Haag, Tobias Horsmann, Stefan Karsch:
A Distributed Virtual Computer Security Lab. CSEDU (1) 2011: 110-119 - [c18]Jens Haag, Tobias Horsmann, Stefan Karsch, Harald P. E. Vranken:
A distributed virtual computer security lab with central authority. CSERC 2011: 89-95
2000 – 2009
- 2008
- [c17]Herman Koppelman, Harald P. E. Vranken:
Experiences with a synchronous virtual classroom in distance education. ITiCSE 2008: 194-198 - 2006
- [c16]Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke:
Fault detection and diagnosis with parity trees for space compaction of test responses. DAC 2006: 1095-1098 - 2004
- [c15]Harald P. E. Vranken, Ferry Syafei Sapei, Hans-Joachim Wunderlich:
Impact of Test Point Insertion on Silicon Area and Timing during Layout. DATE 2004: 810-815 - [c14]Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers:
Efficient Pattern Mapping for Deterministic Logic BIST. ITC 2004: 48-56 - [c13]Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker:
X-Masking During Logic BIST and Its Impact on Defect Coverage. ITC 2004: 442-451 - 2003
- [c12]Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty:
Yield analysis for repairable embedded memories. ETW 2003: 35-40 - [c11]Harald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink:
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume. ITC 2003: 1069-1078 - 2002
- [j4]Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier:
Enhanced Reduced Pin-Count Test for Full-Scan Design. J. Electron. Test. 18(2): 129-143 (2002) - [c10]Harald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich:
Combining deterministic logic BIST with test point insertion. ETW 2002: 105-110 - 2001
- [j3]Gundolf Kiefer, Harald P. E. Vranken, Erik Jan Marinissen, Hans-Joachim Wunderlich:
Application of Deterministic Logic BIST on Industrial Circuits. J. Electron. Test. 17(3-4): 351-362 (2001) - [c9]Alexander Irion, Gundolf Kiefer, Harald P. E. Vranken, Hans-Joachim Wunderlich:
Circuit partitioning for efficient logic BIST synthesis. DATE 2001: 86-91 - [c8]Harald P. E. Vranken, Tom Waayers, Hérvé Fleury, David Lelouvier:
Enhanced reduced pin-count test for full-scan design. ITC 2001: 738-747 - 2000
- [j2]Harald P. E. Vranken:
Debug Facilities in the TriMedia CPU64 Architecture. J. Electron. Test. 16(3): 301-308 (2000) - [c7]Harald P. E. Vranken, Tomás Garciá Garciá, Sjouke Mauw, Loe M. G. Feijs:
IC Design Validation Using Message Sequence Charts. EUROMICRO 2000: 1122- - [c6]Jeroen Voeten, Harald P. E. Vranken:
Behavior-Preserving Transformations for Design-for-Test. EUROMICRO 2000: 1193- - [c5]Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen:
Application of deterministic logic BIST on industrial circuits. ITC 2000: 105-114
1990 – 1999
- 1999
- [c4]Harald P. E. Vranken:
Debug facilities in the TriMedia CPU64 architecture. ETW 1999: 76-81 - [c3]Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-Jan D. Pol, P. Struik, R. H. J. Bloks, Pieter van der Wolf, Harald P. E. Vranken, Frans Sijstermans, M. J. A. Tromp, Andy D. Pimentel:
TriMedia CPU64 Architecture. ICCD 1999: 586-592 - 1997
- [c2]Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers:
Design-For-Debug in Hardware/Software Co-Design. CODES 1997: 35-39 - 1996
- [j1]Harald P. E. Vranken, Marc F. Witteman, Ronald C. van Wuijtswinkel:
Design for Testability in Hardware-Software Systems. IEEE Des. Test Comput. 13(3): 79-87 (1996) - 1994
- [c1]Harald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee:
System-Level Testability of Hardware/Software Systems. ITC 1994: 134-142
Coauthor Index
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