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Journal Articles
- 2023
[j3]Jürgen Maier
, Andreas Steininger, Robert Najvirt:
The Hidden Behavior of a D-Latch. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1660-1670 (2023)- 2020
- [j2]Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid:
A Faithful Binary Circuit Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2784-2797 (2020) - 2016
- [j1]Thomas Polzer, Robert Najvirt, Florian Beck, Andreas Steininger:
On the Appropriate Handling of Metastable Voltages in FPGAs. J. Circuits Syst. Comput. 25(3): 1640020:1-1640020:25 (2016)
Conference and Workshop Papers
- 2023
- [c18]Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer:
ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ASYNC 2023: 48-57 - 2022
- [c17]Florian Huemer, Robert Najvirt, Andreas Steininger:
On SAT-Based Model Checking of Speed-Independent Circuits. DDECS 2022: 100-105 - 2021
- [c16]Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam:
Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC 2021: 25-33 - [c15]Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger:
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD 2021: 541-548 - 2018
- [c14]Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid:
A faithful binary circuit model with adversarial noise. DATE 2018: 1327-1332 - 2017
- [c13]Robert Najvirt, Thomas Polzer, Andreas Steininger:
Measuring Metastability with Free-Running Clocks. ASYNC 2017: 18-24 - 2016
- [c12]Andreas Steininger, Jürgen Maier, Robert Najvirt:
The Metastable Behavior of a Schmitt-Trigger. ASYNC 2016: 57-64 - [c11]Andreas Steininger, Robert Najvirt, Jürgen Maier:
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? DSD 2016: 372-379 - 2015
- [c10]Robert Najvirt, Andreas Steininger:
How to Synchronize a Pausible Clock to a Reference. ASYNC 2015: 9-16 - [c9]Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid:
Towards binary circuit models that faithfully capture physical solvability. DATE 2015: 1455-1460 - [c8]Robert Najvirt, Thomas Polzer, Florian Beck, Andreas Steininger:
Containment of Metastable Voltages in FPGAs. DDECS 2015: 197-202 - [c7]Robert Najvirt, Andreas Steininger:
A pausible clock with crystal oscillator accuracy. ECCTD 2015: 1-4 - [c6]Robert Najvirt, Ulrich Schmid, Michael Hofbauer, Matthias Függer, Thomas Nowak, Kurt Schweiger:
Experimental Validation of a Faithful Binary Circuit Model. ACM Great Lakes Symposium on VLSI 2015: 355-360 - [c5]Robert Najvirt, Andreas Steininger:
A versatile and reliable glitch filter for clocks. PATMOS 2015: 140-147 - 2014
- [c4]Robert Najvirt, Andreas Steininger:
Equivalence of clock gating and synchronization with applicability to GALS communication. PATMOS 2014: 1-8 - 2013
- [c3]Robert Najvirt, Syed Rameez Naqvi, Andreas Steininger:
Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. ASYNC 2013: 115-123 - [c2]Syed Rameez Naqvi, Robert Najvirt, Andreas Steininger:
A Multi-Credit Flow Control scheme for asynchronous NoCs. DDECS 2013: 153-158 - 2012
- [c1]Jakob Lechner, Robert Najvirt:
A Generic Architecture for Robust Asynchronous Communication Links. PATMOS 2012: 121-130
Informal and Other Publications
- 2020
- [i4]Andreas Steininger, Jürgen Maier, Robert Najvirt:
The Metastable Behavior of a Schmitt-Trigger. CoRR abs/2006.08319 (2020) - [i3]Andreas Steininger, Robert Najvirt, Jürgen Maier:
Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? CoRR abs/2006.08415 (2020) - [i2]Matthias Függer, Jürgen Maier, Robert Najvirt, Thomas Nowak, Ulrich Schmid:
A Faithful Binary Circuit Model with Adversarial Noise. CoRR abs/2006.08485 (2020) - 2014
- [i1]Matthias Függer, Robert Najvirt, Thomas Nowak, Ulrich Schmid:
Faithful Glitch Propagation in Binary Circuit Models. CoRR abs/1406.2544 (2014)
Coauthor Index
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