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A. V. AnanthaLakshmi

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Journal Articles

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2017
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A. V. AnanthaLakshmi, Gnanou Florence Sudha:
Design of a reversible floating-point square root using modified non-restoring algorithm. Microprocess. Microsystems 50: 39-53 (2017)
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A. V. AnanthaLakshmi, Gnanou Florence Sudha:
A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications. Microprocess. Microsystems 51: 366-385 (2017)
2015
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A. V. AnanthaLakshmi, G. Florence Sudha:
Design of an efficient reversible single precision floating point adder. Int. J. Comput. Intell. Stud. 4(1): 2-30 (2015)

Conference and Workshop Papers

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2013
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A. V. AnanthaLakshmi, G. Florence Sudha:
Transistor Representation of a Low-Power Reversible 32-Bit Comparator. ICACNI 2013: 67-79
2012
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A. V. AnanthaLakshmi, G. Florence Sudha:
Design of a Novel Reversible Full Adder and Reversible Full Subtractor. ACITY (3) 2012: 623-632

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