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2020 – today
- 2024
[j9]Agata Iesurum
, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua:
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs. IEEE J. Solid State Circuits 59(1): 294-306 (2024)- 2023
- [j8]Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua:
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 607-617 (2023) - 2022
- [j7]Fabio Quadrelli, Davide Manente, David Seebacher, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua:
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications. IEEE J. Solid State Circuits 57(7): 1968-1981 (2022) - [j6]Lorenzo Tomasin, Pietro Andreani, Giovanni Boi, Fabio Padovan, Andrea Bevilacqua:
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise. IEEE J. Solid State Circuits 57(9): 2802-2811 (2022) - [c10]Agata Iesurum, Davide Manente, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua:
A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS. ESSCIRC 2022: 385-388 - 2021
- [c9]Davide Manente, Fabio Quadrelli, Fabio Padovan, Matteo Bassi, Andrea Mazzanti, Andrea Bevilacqua:
A 22-31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS. ESSCIRC 2021: 283-286 - 2020
- [j5]Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Andrea Bevilacqua:
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects. IEEE J. Solid State Circuits 55(7): 1842-1853 (2020)
2010 – 2019
- 2019
- [c8]Alessandro Franceschin, Pietro Andreani, Fabio Padovan, Matteo Bassi, Roberto Nonis, Andrea Bevilacqua:
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion. ESSCIRC 2019: 45-48 - [c7]Matteo Bassi, Giovanni Boi, Fabio Padovan, Jonas Fritzin, Stefano Di Martino, Daniel Knauder, Andrea Bevilacqua:
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS. ESSCIRC 2019: 107-110 - 2018
- [j4]Alessandro Franceschin, Fabio Padovan, Roberto Nonis, Andrea Bevilacqua:
On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 657-661 (2018) - [c6]Fabio Padovan, Fabio Quadrelli, Matteo Bassi, Marc Tiebout, Andrea Bevilacqua:
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations. ISSCC 2018: 376-378 - 2017
- [c5]Fabio Boscolo, Fabio Padovan, Fabio Quadrelli, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset. ESSCIRC 2017: 91-94 - 2016
- [j3]Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation. IEEE J. Solid State Circuits 51(7): 1525-1536 (2016) - [j2]Stefano Brenna, Fabio Padovan, Andrea Neviani, Andrea Bevilacqua, Andrea Bonfanti, Andrea L. Lacaita:
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 63-II(6): 528-532 (2016) - [c4]Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers. ESSCIRC 2016: 363-366 - 2015
- [j1]Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani:
Design of Low-Noise K-Band SiGe Bipolar VCOs: Theory and Implementation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 607-615 (2015) - [c3]Fabio Padovan, Marc Tiebout, Andrea Neviani, Andrea Bevilacqua:
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation. ESSCIRC 2015: 56-59 - 2014
- [c2]Fabio Padovan, Andrea Bevilacqua, Andrea Neviani:
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS. ESSCIRC 2014: 287-290 - 2012
- [c1]Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua, Andrea Neviani:
A SiGe bipolar VCO for backhaul E-band communication systems. ESSCIRC 2012: 402-405
Coauthor Index
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