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2020 – today
- 2021
[c6]Gaurav Malhotra, Jalil Kamali, Amir Amirkhany:
Baud rate pattern-adaptable dual loop clock recovery for high speed serial links. ACSCC 2021: 43-48- 2020
- [d1]Vijayaraghavan Thirumalai, Javier Ribera
, Jie Xiang, Junbin Zhang, Maryam Azimi, Jalil Kamali, Panos Nasiopoulos:
UBC2019 - A dataset of subjective image quality of head-mounted displays. Zenodo, 2020
2010 – 2019
- 2019
- [c5]Anup P. Jose, Valentin Abramzon, Mohamed Elzeftawi, Michael Wang, Kyunglok Kim, Younghoon Song, Shiva Moballegh, Jalil Kamali, Amir Amirkhany:
A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. CICC 2019: 1-4 - [c4]Gaurav Malhotra, Jalil Kamali:
Symbol spaced clock recovery for high speed links. ICSPCS 2019: 1-5 - 2016
- [c3]Mohammad Hekmat, Sanquan Song, Nancy Jaffari, Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong:
23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays. ISSCC 2016: 402-403 - 2015
- [c2]Gaurav Malhotra, Jalil Kamali:
BER analysis of high speed links with nonlinearity. ACSSC 2015: 635-640 - 2012
- [c1]Jafar Savoj, Kenny C.-H. Hsieh, Parag Upadhyaya, Fu-Tai An, Jay Im, Xuewen Jiang, Jalil Kamali, Kang Wei Lai, Zhaoyin Daniel Wu, Elad Alon, Ken Chang:
Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. CICC 2012: 1-4
2000 – 2009
- 2005
- [j1]Guozhu Long, Jalil Kamali, Amir H. Fazlollahi, Vinay R. Rao:
Competition stimulates technology advances: experiences from ADSL development in Japan. IEEE Commun. Mag. 43(9): 110-115 (2005)
Coauthor Index
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