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ORCIDYoun Sung Park
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- affiliation: University of Michigan, Ann Arbor, MI, USA
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2020 – today
- 2023
[c8]David Garrett, Youn Sung Park, Seongjong Kim, Jay Sharma, Wenbin Huang, Majid Shaghaghi, Vinay Parthasarathy, Stephen Gibellini, Stephen Bailey, Mallik Moturi, Pieter Vorenkamp, Kurt Busch, Jeremy Holleman, Behrooz Javid, Alireza Yousefi, Mohsen Judy, Atul Gupta:
A 1mW Always-on Computer Vision Deep Learning Neural Decision Processor. ISSCC 2023: 158-159
2010 – 2019
- 2015
- [j3]Youn Sung Park, Yaoyu Tao, Zhengya Zhang
:
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. IEEE J. Solid State Circuits 50(2): 464-475 (2015) - 2014
- [j2]Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang:
Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. IEEE J. Solid State Circuits 49(3): 783-794 (2014) - [c7]Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang:
A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. VLSIC 2014: 1-2 - 2013
- [j1]Zhiyoong Foo, David Devescery, Mohammad Hassan Ghaed, Inhee Lee, Abishek Madhavan, Youn Sung Park, Aswin S. Rao, Zach Renner, Nathan Roberts, Aaron Schulman, Vikas Vinay, Michael Wieckowski, Dongmin Yoon, Cliff Schmidt, Thomas Schmid, Prabal Dutta, Peter M. Chen, David T. Blaauw:
A Low-Cost Audio Computer for Information Dissemination Among Illiterate People Groups. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2039-2050 (2013) - [c6]Youn Sung Park, Yaoyu Tao, Zhengya Zhang:
A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. ISSCC 2013: 422-423 - 2012
- [c5]Zhiyoong Foo, David Devescery, Mohammad Hassan Ghaed, Inhee Lee, Abishek Madhavan, Youn Sung Park, Aswin S. Rao, Zach Renner, Nathan Roberts, Aaron Schulman, Vikas Vinay, Michael Wieckowski, Dongmin Yoon, Cliff Schmidt, Thomas Schmid, Prabal Dutta, Peter M. Chen, David T. Blaauw:
A low-cost audio computer for information dissemination among illiterate people groups. CICC 2012: 1-4 - [c4]Haoran Li, Youn Sung Park, Zhengya Zhang:
Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. FPGA 2012: 167-170 - [c3]Yaoyu Tao, Youn Sung Park, Zhengya Zhang:
High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. ISCAS 2012: 2625-2628 - [c2]Youn Sung Park, David T. Blaauw, Dennis Sylvester, Zhengya Zhang:
A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM. VLSIC 2012: 114-115 - 2010
- [c1]Zhiyoong Foo, David Devescery, Thomas Schmid, Nathan Clark, R. Frank, Mohammad Hassan Ghaed, Ye-Sheng Kuo, Inhee Lee, Youn Sung Park, Zach Renner, Nathaniel Slottow, Vikas Vinay, Michael Wieckowski, Dongmin Yoon, Cliff Schmidt, David T. Blaauw, Peter M. Chen, Prabal Dutta:
A case for custom silicon in enabling low-cost information technology for developing regions. ACM DEV 2010: 22
Coauthor Index
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