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Shiva Madishetty

Shiva Kumar Madishetty

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Journal Articles

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2014
[j3]
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Shiva Kumar Madishetty, Arjuna Madanayake, Renato J. Cintra, Vassil S. Dimitrov, Dale H. Mugler:
Algebraic integer architecture with minimum adder count for the 2-D Daubechies 4-tap filters banks. Multidimens. Syst. Signal Process. 25(4): 829-845 (2014)
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Shiva Kumar Madishetty, Arjuna Madanayake, Renato J. Cintra, Vassil S. Dimitrov:
Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 1984-1993 (2014)
2013
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Shiva Kumar Madishetty, Arjuna Madanayake, Renato J. Cintra, Vassil S. Dimitrov, Dale H. Mugler:
VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(6): 1455-1468 (2013)

Conference and Workshop Papers

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2012
[c1]
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Shiva Madishetty, Arjuna Madanayake, Renato J. Cintra, Dale H. Mugler, Vassil S. Dimitrov:
Error-free VLSI architecture for the 2-D Daubechies 4-tap filter using algebraic integers. ISCAS 2012: 1484-1487

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