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Gerd Ritter

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2000 – 2009

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2001
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Gerd Ritter:
Formal sequential equivalence checking of digital systems by symbolic simulation. Darmstadt University of Technology, Germany, 2001, pp. 1-156
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Claudia Blank, Hans Eveking, Jens Levihn, Gerd Ritter:
Symbolic simulation techniques-state-of-the-art and applications. HLDVT 2001: 45-50
2000
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Gerd Ritter:
Sequential Equivalence Checking by Symbolic Simulation. FMCAD 2000: 423-442
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Claudia Blank, Gerd Ritter, Holger Hinrichsen, Hans Eveking:
Formale Verifikation der Register-Allokation. MBMV 2000: 27-35

1990 – 1999

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1999
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Gerd Ritter, Holger Hinrichsen, Hans Eveking:
Formal Verification of Descriptions with Distinct Order of Memory Operations. ASIAN 1999: 308-321
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Gerd Ritter, Hans Eveking, Holger Hinrichsen:
Formal Verification of Designs with Complex Control by Symbolic Simulation. CHARME 1999: 234-249
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Hans Eveking, Holger Hinrichsen, Gerd Ritter:
Automatic Verification of Scheduling Results in High-Level Synthesis. DATE 1999: 59-64
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Holger Hinrichsen, Gerd Ritter, Hans Eveking:
Automatische Synthese und Verifikation von RISC-Prozessoren. MBMV 1999: 1-10

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