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ORCIDKedarnath J. Balakrishnan
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Journal Articles
- 2009
[j5]Kedarnath J. Balakrishnan, Grady Giles, James Wingfield:
Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor. IEEE Des. Test Comput. 26(1): 52-59 (2009)- 2008
- [j4]Seongmoon Wang, Kedarnath J. Balakrishnan, Wenlong Wei:
X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors. IEEE Trans. Computers 57(7): 978-989 (2008) - 2007
- [j3]Kedarnath J. Balakrishnan, Nur A. Touba:
Relationship Between Entropy and Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 386-395 (2007) - 2006
- [j2]Kedarnath J. Balakrishnan, Nur A. Touba:
Improving Linear Test Data Compression. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1227-1237 (2006) - 2004
- [j1]Kedarnath J. Balakrishnan, Nur A. Touba:
Matrix-based software test data decompression for systems-on-a-chip. J. Syst. Archit. 50(5): 247-256 (2004)
Conference and Workshop Papers
- 2009
- [c17]Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield:
Test access mechanism for multiple identical cores. ITC 2009: 1-10 - 2008
- [c16]Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield:
Test Access Mechanism for Multiple Identical Cores. ITC 2008: 1-10 - 2007
- [c15]Quming Zhou, Kedarnath J. Balakrishnan:
Test cost reduction for SoC using a combined approach to test data compression and test scheduling. DATE 2007: 39-44 - [c14]Kedarnath J. Balakrishnan:
Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding. VLSI Design 2007: 345-350 - [c13]Kedarnath J. Balakrishnan, Lei Fang:
RTL Test Point Insertion to Reduce Delay Test Volume. VTS 2007: 325-332 - 2006
- [c12]Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar:
Efficient unknown blocking using LFSR reseeding. DATE 2006: 1051-1052 - [c11]Kedarnath J. Balakrishnan, Seongmoon Wang, Srimat T. Chakradhar:
PIDISC: Pattern Independent Design Independent Seed Compression Technique. VLSI Design 2006: 811-817 - 2005
- [c10]Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil:
Compressing Functional Tests for Microprocessors. Asian Test Symposium 2005: 428-433 - [c9]Kedarnath J. Balakrishnan:
Emerging Techniques for Test Data Compression. Asian Test Symposium 2005: 462 - [c8]Kedarnath J. Balakrishnan, Nur A. Touba:
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. DATE 2005: 1130-1135 - [c7]Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar:
XWRC: externally-loaded weighted random pattern testing for input test data compression. ITC 2005: 10 - 2004
- [c6]Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan:
Re-configurable embedded core test protocol. ASP-DAC 2004: 234-237 - [c5]Kedarnath J. Balakrishnan, Nur A. Touba:
Relating entropy theory to test data compression. ETS 2004: 94-99 - [c4]Kedarnath J. Balakrishnan, Nur A. Touba:
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. ITC 2004: 936-944 - 2003
- [c3]Kedarnath J. Balakrishnan, Nur A. Touba:
Scan-Based BIST Diagnosis Using an Embedded Processor. DFT 2003: 209-216 - [c2]Kedarnath J. Balakrishnan, Nur A. Touba:
Deterministic Test Vector Decompression in Software Using Linear Operations. VTS 2003: 225-231 - 2002
- [c1]Kedarnath J. Balakrishnan, Nur A. Touba:
Matrix-Based Test Vector Decompression Using an Embedded Processor. DFT 2002: 159-165
Coauthor Index
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