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2020 – today
- 2023
[c4]Kritchawat Waitchasarn, Arthit Thongtak, Taratip Suwannasart:
Generating Robot Framework Test Scripts from User Stories and Scenarios for Web Application Testing. ICCCS 2023: 795-801- 2022
- [j5]Chanon Dechsupa
, Wiwat Vatanawood, Arthit Thongtak:
Stepwise Verification for the BPMN With Timed and Stochastic Process Using a Colored Generalized Stochastic Petri Net. IEEE Access 10: 42983-43002 (2022) - 2021
- [j4]Chanon Dechsupa, Wiwat Vatanawood, Worawit Poolsawasdi, Arthit Thongtak:
An Applying Colored Petri Net for Computerized Accounting System and Ledger Accounts Instruction. Comput. 10(12): 169 (2021)
2010 – 2019
- 2019
- [j3]Chanon Dechsupa, Wiwat Vatanawood, Arthit Thongtak:
Hierarchical Verification for the BPMN Design Model Using State Space Analysis. IEEE Access 7: 16795-16815 (2019) - 2018
- [j2]Chanon Dechsupa, Wiwat Vatanawood, Arthit Thongtak:
Transformation of the BPMN Design Model into a Colored Petri Net Using the Partitioning Approach. IEEE Access 6: 38421-38436 (2018) - 2016
- [c3]Patsakorn Rittitum, Wiwat Vatanawood, Arthit Thongtak:
Digital scrum board using leap motion. ICIS 2016: 1-4
2000 – 2009
- 2008
- [c2]Thanasin Bunnam, Arthit Thongtak:
An Approach for the Delay Simulation of D-Inverter in C-Ternary Logic Circuits. CDES 2008: 224-228 - [c1]Sufian Sudeng, Arthit Thongtak:
Template Based: A Novel STG Based Logic Synthesis for Asynchronous Control Circuits. World Congress on Engineering (Selected Papers) 2008: 59-74
1990 – 1999
- 1998
- [j1]Arthit Thongtak, Takashi Nanya:
Stuck-at-fault testing for quasi-delay-insensitive logic circuits. Syst. Comput. Jpn. 29(2): 19-27 (1998)
Coauthor Index
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