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ORCIDMarcelo Antonio Pavanello
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Journal Articles
- 2017
[j11]Bruna Cardoso Paz, Renan Trevisoli Doria, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello:
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. Microelectron. Reliab. 79: 111-118 (2017)- 2016
- [j10]Rafael Assalti, Lígia Martins d'Oliveira, Marcelo Antonio Pavanello, Denis Flandre
, Michelly de Souza:
Experimental and simulation analysis of electrical characteristics of common-source current mirrors implemented with asymmetric self-cascode silicon-on-insulator n-channel metal-oxide-semiconductor field-effect transistors. IET Circuits Devices Syst. 10(4): 349-355 (2016) - [j9]Magali Estrada, M. Rivas, Ivan Garduño, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello, Israel Mejia, M. A. Quevedo-Lopez:
Temperature dependence of the electrical characteristics up to 370 K of amorphous In-Ga-ZnO thin film transistors. Microelectron. Reliab. 56: 29-33 (2016) - [j8]Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello:
Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectron. Reliab. 63: 1-10 (2016) - 2013
- [j7]Michelly de Souza, Bruna Cardoso Paz, Denis Flandre, Marcelo Antonio Pavanello:
Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs. Microelectron. Reliab. 53(6): 848-855 (2013) - 2012
- [j6]Renan Trevisoli Doria, João Antonio Martino, Eddy Simoen, Cor Claeys, Marcelo Antonio Pavanello:
An analytic method to compute the stress dependence on the dimensions and its influence in the characteristics of triple gate devices. Microelectron. Reliab. 52(3): 519-524 (2012) - 2011
- [j5]Denise C. Lugo Muñoz, Juan Muci, Adelmo Ortiz-Conde, Francisco J. García-Sánchez, Michelly de Souza, Marcelo Antonio Pavanello:
An explicit multi-exponential model for semiconductor junctions with series and shunt resistances. Microelectron. Reliab. 51(12): 2044-2048 (2011) - 2008
- [j4]Rodrigo Trevisoli Doria, Antonio Cerdeira, Jean-Pierre Raskin, Denis Flandre, Marcelo Antonio Pavanello:
Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation. Microelectron. J. 39(12): 1663-1670 (2008) - 2006
- [j3]Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Denis Flandre:
Gain improvement in operational transconductance amplifiers using Graded-Channel SOI nMOSFETS. Microelectron. J. 37(1): 31-37 (2006) - [j2]Marcelo Antonio Pavanello, Paula Ghedini Der Agopian, João Antonio Martino, Denis Flandre:
Cryogenic operation of graded-channel silicon-on-insulator nMOSFETs for high performance analog applications. Microelectron. J. 37(2): 137-144 (2006) - [j1]Milene Galeti, Marcelo Antonio Pavanello, João Antonio Martino:
Evaluation of graded-channel SOI MOSFET operation at high temperatures. Microelectron. J. 37(7): 601-607 (2006)
Conference and Workshop Papers
- 2021
- [c7]Michelly de Souza, Sylvain Barraud, Mikaël Cassé, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello:
Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. ESSDERC 2021: 223-226 - 2019
- [c6]Wladek Grabinski, Ahmed Abo-Elhadid, Marek Mierzwinski, Laurent Lemaitre, Mike Brinson, Christophe Lallement, Jean-Michel Sallese, Sadayuki Yoshitomi, Paul Malisse, Henri Oguey, Stefan Cserveny, Marcelo Antonio Pavanello, Christian C. Enz, François Krummenacher, Eric A. Vittoz, Michelly de Souza, Daniel Tomaszewski, Jolanta Malesinska, Grzegorz Gluszko, Matthias Bucher, Nikolaos Makris, Aristeidis Nikolaou:
FOSS EKV2.6 Verilog-A Compact MOSFET Model. ESSDERC 2019: 190-193 - [c5]Renan Trevisoli, Rodrigo Trevisoli Doria, Sylvain Barraud, Marcelo Antonio Pavanello:
Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors. ESSDERC 2019: 194-197 - 2017
- [c4]Renan Trevisoli Doria, Rodrigo Trevisoli Doria, Michelly de Souza, Marcelo Antonio Pavanello, Sylvain Barraud:
A new method for junctionless transistors parameters extraction. ESSDERC 2017: 66-69 - 2016
- [c3]Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot:
Analog performance of strained SOI nanowires down to 10K. ESSDERC 2016: 222-225 - 2003
- [c2]Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, Stephane Adriaensen, Denis Flandre:
Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. SBCCI 2003: 26- - 2001
- [c1]Marcelo Antonio Pavanello, João Antonio Martino, Denis Flandre:
Analog Circuit Design Using Graded-Channel SOI NMOSFETS. SBCCI 2001: 130-135
Coauthor Index
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