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Journal Articles
- 2013
[j1]Awais Hussain Sani, Philippe Coussy, Cyrille Chavet:
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm. IEEE Trans. Signal Process. 61(16): 4127-4140 (2013)
Conference and Workshop Papers
- 2016
- [c10]Awais Sani, Philippe Coussy, Cyrille Chavet:
A dynamically reconfigurable ECC decoder architecture. DATE 2016: 1437-1440 - [c9]Awais Hussain Sani, José Luis Núñez-Yáñez
:
Energy proportional computing with OpenCL on a FPGA-based overlay architecture. NORCAS 2016: 1-6 - 2015
- [c8]Saeed Ur Reehman, Cyrille Chavet, Philippe Coussy, Awais Sani:
In-place memory mapping approach for optimized parallel hardware interleaver architectures. DATE 2015: 896-899 - 2014
- [c7]Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy:
Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures. ICASSP 2014: 5036-5040 - 2013
- [c6]Saeed-ur Rehman, Awais Sani, Philippe Coussy, Cyrille Chavet:
On-chip implementation of memory mapping algorithm to support flexible decoder architecture. ICASSP 2013: 2751-2755 - 2012
- [c5]Oscar Sanchez, Michel Jézéquel, Saeed-ur Rehman, Awais Sani, Cyrille Chavet, Philippe Coussy, Christophe Jégo:
A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders. SiPS 2012: 288-293 - 2011
- [c4]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
A methodology based on Transportation problem modeling for designing parallel interleaver architectures. ICASSP 2011: 1613-1616 - [c3]Ghulam Abbas, Nacer Abouchi, Awais Sani, Cyril Condemine:
Design and analysis of fuzzy logic based robust PID controller for PWM-based switching converter. ISCAS 2011: 777-780 - [c2]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture. ISCAS 2011: 1720-1723 - 2010
- [c1]Awais Sani, Philippe Coussy, Cyrille Chavet, Eric Martin:
Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach. ICECS 2010: 466-469
Coauthor Index
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