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Journal Articles
- 2016
[j6]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Tsai, Wu-Tung Cheng:
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects. IEEE Des. Test 33(2): 9-16 (2016)- [j5]Shi-Yu Huang, Chih-Chieh Cheng, Meng-Ting Tsai, Kuan-Chen Huang, Kun-Han Tsai, Wu-Tung Cheng:
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC. IEEE Des. Test 33(6): 23-30 (2016) - 2015
- [j4]Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1836-1846 (2015) - [j3]Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 2039-2048 (2015) - 2013
- [j2]Faa-Jeng Lin
, Ying-Chih Hung, Meng-Ting Tsai:
Fault-Tolerant Control for Six-Phase PMSM Drive System via Intelligent Complementary Sliding-Mode Control Using TSKFNN-AMF. IEEE Trans. Ind. Electron. 60(12): 5747-5762 (2013) - 2006
- [j1]Ching-Yuan Yang, Meng-Ting Tsai:
High-Frequency Low-Noise Voltage-Controlled LC-Tank Oscillators Using a Tunable Inductor Technique. IEICE Trans. Electron. 89-C(11): 1567-1574 (2006)
Conference and Workshop Papers
- 2015
- [c6]Shi-Yu Huang, Meng-Ting Tsai, Kun-Han Hans Tsai, Wu-Tung Cheng:
Feedback-bus oscillation ring: a general architecture for delay characterization and test of interconnects. DATE 2015: 924-927 - [c5]Meng-Ting Tsai, Shi-Yu Huang, Kun-Han Tsai, Wu-Tung Cheng:
Monitoring the delay of long interconnects via distributed TDC. ITC 2015: 1-9 - 2007
- [c4]Meng-Ting Tsai, Ching-Yuan Yang:
A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications. ICECS 2007: 1384-1387 - 2006
- [c3]Meng-Ting Tsai, Ching-Yuan Yang:
A frequency synthesizer realized by a transformer-based voltage-controlled oscillator for IEEE 802.11a/b/g channels. ISCAS 2006 - [c2]Jun-Hong Weng, Meng-Ting Tsai, Jung-Mao Lin, Ching-Yuan Yang:
A 1.8-Gb/s burst-mode clock and data recovery circuit with a 1/4-rate clock technique. ISCAS 2006 - 2005
- [c1]Ching-Yuan Yang, Jen-Wen Chen, Meng-Ting Tsai:
A high-frequency phase-compensation fractional-N frequency synthesizer. ISCAS (5) 2005: 5091-5094
Informal and Other Publications
- 2024
- [i1]Tien-Hong Lo, Meng-Ting Tsai, Berlin Chen:
Zero-Shot Text-to-Speech as Golden Speech Generator: A Systematic Framework and its Applicability in Automatic Pronunciation Assessment. CoRR abs/2409.07151 (2024)
Coauthor Index
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