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ORCIDSudarshan Bahukudumbi
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2000 – 2009
- 2009
[j5]Sudarshan Bahukudumbi, Krishnendu Chakrabarty
:
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 111-120 (2009)- [j4]Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar:
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 587-592 (2009) - [j3]Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In. IEEE Trans. Very Large Scale Integr. Syst. 17(12): 1730-1741 (2009) - 2008
- [b1]Sudarshan Bahukudumbi:
Wafer-Level Testing and Test Planning for Integrated Circuits. Duke University, Durham, NC, USA, 2008 - [j2]Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Trans. Design Autom. Electr. Syst. 13(3): 53:1-53:19 (2008) - [c7]Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Power Management for Wafer-Level Test During Burn-In. ATS 2008: 231-236 - [c6]Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz:
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs. DATE 2008: 1103-1106 - [c5]Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In. VTS 2008: 193-198 - 2007
- [j1]Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Wafer-Level Modular Testing of Core-Based SoCs. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1144-1154 (2007) - [c4]Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar:
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ASP-DAC 2007: 823-828 - [c3]Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs. VLSI Design 2007: 459-464 - 2006
- [c2]Sudarshan Bahukudumbi, Krishnendu Chakrabarty:
Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs. ITC 2006: 1-10 - 2005
- [c1]Sudarshan Bahukudumbi, Krishna Bharath:
A Low Overhead High Speed Histogram Based Test Methodology for Analog Circuits and IP Cores. VLSI Design 2005: 804-807
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