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ORCIDJack S. N. Jean
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- affiliation: Wright State University, Fairborn, Ohio, USA
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2010 – 2019
- 2012
[j10]Fei Wang, Jack S. N. Jean:
Architecture and operating system support for two-dimensional runtime partial reconfiguration. J. Supercomput. 59(2): 610-635 (2012)- 2010
- [c15]Srikanth Nadella, Andrew Dittes, Jack S. N. Jean:
Parameterized AND-OR Trees for FPGA Design Space Exploration. ERSA 2010: 255-258
2000 – 2009
- 2006
- [c14]Fei Wang, Jack S. N. Jean:
Architectural Support for Runtime 2D Partial Reconfiguration. ERSA 2006: 231-236 - 2005
- [c13]Fei Wang, Jack S. N. Jean, Shuxia Sun:
Aspect Ratio Effects on Reconfigurable Computing. ERSA 2005: 71-77 - 2004
- [c12]Xinzhong Guo, Jack S. N. Jean:
Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers. ERSA 2004: 305-306 - 2003
- [j9]Xuejun Liang, Jack S. N. Jean:
Mapping of generalized template matching onto reconfigurable computers. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 485-498 (2003) - [c11]Jack S. N. Jean, Xinzhong Guo, Fei Wang, Lei Song, Ying Zhang:
A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers. Engineering of Reconfigurable Systems and Algorithms 2003: 51-57 - 2001
- [j8]Xuejun Liang, Jack S. N. Jean, Karen A. Tomko
:
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. J. Supercomput. 19(1): 77-91 (2001) - 2000
- [j7]Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko, Yan Wang:
Automatic Target Recognition with Dynamic Reconfiguration. J. VLSI Signal Process. 25(1): 39-53 (2000) - [c10]Xuejun Liang, Jack S. N. Jean:
Interface Design for the Mapping of Generalized Template Matching on Reconfigurable Systems. PDPTA 2000
1990 – 1999
- 1999
- [j6]Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Jignesh Shah, Robert Cook:
Dynamic Reconfiguration to Support Concurrent Applications. IEEE Trans. Computers 48(6): 591-602 (1999) - [j5]Joseph A. Fernando, Jack S. N. Jean:
Processor array design with FPGA area constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 253-264 (1999) - [j4]Hong K. Kim, Jack S. N. Jean:
Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation. VLSI Design 9(3): 253-270 (1999) - [c9]Jack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko:
Accelerating an IR Automatic Target Recognition Application with FPGAs. FCCM 1999: 290-291 - [c8]Jack S. N. Jean, Xuejun Liang, Karen A. Tomko:
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems. PDPTA 1999: 1111-1117 - 1998
- [c7]Jack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah:
Dynamic Reconfiguration to Support Concurrent Applications. FCCM 1998: 302-303 - [c6]Hong K. Kim, Jack S. N. Jean:
Parallel Optimistic Logic Simulation with Event Lookahead. ICPP 1998: 20-27 - 1996
- [c5]Hong K. Kim, Jack S. N. Jean:
Concurrency Preserving Rartitioning (CPP) for Parallel Logic Simulation. Workshop on Parallel and Distributed Simulation 1996: 98-105 - 1995
- [c4]Joseph A. Fernando, Jack S. N. Jean:
Interfacing FPGA/VLSI Processor Arrays. ASAP 1995: 230-237 - 1994
- [j3]Jin Wang, Jack S. N. Jean:
Segmentation of merged characters by neural networks and shortest path. Pattern Recognit. 27(5): 649-658 (1994) - [j2]Jack S. N. Jean, Jin Wang:
Weight smoothing to improve network generalization. IEEE Trans. Neural Networks 5(5): 752-763 (1994) - 1993
- [j1]Jin Wang, Jack S. N. Jean:
Resolving multifont character confusion with neural networks. Pattern Recognit. 26(1): 175-187 (1993) - [c3]Jin Wang, Jack S. N. Jean:
Segmentation of Merged Characters by Neural Networks and Shortest-Path. SAC 1993: 762-769 - 1990
- [c2]Jack S. N. Jean:
Fault-tolerant array processors using N-and-half-track switches. ASAP 1990: 426-437 - [c1]Jack S. N. Jean:
A new distance measure for binary images. ICASSP 1990: 2061-2064
Coauthor Index
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