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SIGARCH Computer Architecture News, Volume 15
Volume 15, Number 1, March 1987
- Robert H. Halstead Jr.:
Overview of concert multilisp: a multiprocessor symbolic computing system. 5-14 - Dave Patterson:
A progress report on SPUR: February 1, 1987. 15-21 - Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy:
Aquarius. 22-34 - Madhur Kohli, Mark E. Giuliano, Jack Minker:
An overview of the PRISM project. 35-42 - Manuel V. Hermenegildo, Richard A. Warren:
Designing a high performance parallel logic programming system. 43-52 - Jonathan W. Mills:
Coming to grips with a RISC: a report of the progress of the LOW RISC design group. 53-62 - Brian Short:
Use of instruction set simulators to evaluate the LOW RISC. 63-67 - Kurt M. Gutzmann:
Optimal dimension of hypercubes for sorting. 68-72 - Gilman D. Chesley:
Addressable WSI: a non-redundant approach. 73-80 - Nripendra N. Biswas, Sampalli Srinivas, Trishala Dharanendra:
A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture. 81-87
Volume 15, Number 2, June 1987
Currently Not Available
Volume 15, Number 3, June 1987
- Matthew Moore, Charles E. McDowell:
Bi-directional networks for large parallel processors. 3-4 - Ian Kaplan:
The LDF 100: a large grain dataflow parallel processor. 5-12 - Stanley E. Lass:
Wide channel computers. 13-16 - Reinder J. Bril:
An implementation independent approach to cache memories. 17-24 - Reinder J. Bril:
On cacheability of lock-variables in tightly coupled multiprocessor systems. 25-32
Volume 15, Number 4, September 1987
- J. K. Iliffe:
A forward-looking method of Cache memory control. 4-10 - Amitava Bandyopadhyay, Yuan F. Zheng:
Combining both microcode and hardwired control in RISC. 11-15 - Martin Dowd:
An example RISC vector machine architecture. 16-22 - Sanjiv K. Bhatia, A. Gregory Starling:
Multilayered illiac network scheme. 23-31 - Lothar Nowak:
SAMP: a general purpose processor based on a self-timed VLIW structure. 32-39 - Peter J. Ashenden, Chris J. Barter, Chris D. Marlin:
The Leopard workstation project. 40-51 - Y. Paul Chiang, Mark L. Manwaring:
Direct execution lisp and cell memory. 52-57 - J. M. Terry:
Flow-control machines: the structured execution architecture (SXA). 58-69
Volume 15, Number 5, October 1987
- Randy H. Katz, Martin Freeman:
Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987. ACM Press 1987, ISBN 0-8186-0805-6 [contents]
Volume 15, Number 6, December 1987
- Edward E. E. Frietman, Anthonie B. Ruighaver:
An electro-optic data communication system for the Delft parallel processor. 2-8 - G. B. Shippen, James K. Archibald:
A tagged token dataflow machine for computing small, iterative algorithms. 9-18
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