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ORCIDACM Journal on Emerging Technologies in Computing Systems, Volume 15
Volume 15, Number 1, February 2019
- Edoardo Fusella, Mahdi Nikdast, Ian O'Connor
, José Flich, Sudeep Pasricha:
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. 1:1-1:2 - Mourad Dridi, Stéphane Rubini, Mounir Lallali, Martha Johanna Sepúlveda Flórez, Frank Singhoff, Jean-Philippe Diguet:
Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems. 2:1-2:37 - Mladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla:
Time-Randomized Wormhole NoCs for Critical Applications. 3:1-3:23 - Ahmed Louri, Jacques Henri Collet, Avinash Karanth:
Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs. 4:1-4:16 - P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J.:
Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement. 5:1-5:23 - Kanchan Manna, Chatla Swami Sagar, Santanu Chattopadhyay, Indranil Sengupta:
Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems. 6:1-6:27 - Sneha N. Ved, Sarabjeet Singh, Joycee Mekie:
PANE: Pluggable Asynchronous Network-on-Chip Simulator. 7:1-7:27 - Janibul Bashir, Eldhose Peter, Smruti R. Sarangi:
BigBus: A Scalable Optical Interconnect. 8:1-8:24
- Zhen Xu, Xuhao Chen, Jie Shen, Yang Zhang, Cheng Chen, Canqun Yang:
GARDENIA: A Graph Processing Benchmark Suite for Next-Generation Accelerators. 9:1-9:13 - Su-Kyung Yoon, Young-Sun Youn, Bernd Burgstaller, Shin-Dug Kim:
Self-learnable Cluster-based Prefetching Method for DRAM-Flash Hybrid Main Memory Architecture. 10:1-10:21 - Xiaotong Cui, Jeff Jun Zhang, Kaijie Wu, Siddharth Garg, Ramesh Karri:
Split Manufacturing-Based Register Transfer-Level Obfuscation. 11:1-11:22 - Bingzhe Li, Yaobin Qin, Bo Yuan, David J. Lilja:
Neural Network Classifiers Using a Hardware-Based Approximate Activation Function with a Hybrid Stochastic Multiplier. 12:1-12:21 - Zhou Zhao, Ashok Srivastava, Lu Peng, Qing Chen:
Long Short-Term Memory Network Design for Analog Computing. 13:1-13:27
Volume 15, Number 2, June 2019
- Jae-sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning. 14:1-14:2 - Weijia Wang, Bill Lin:
Trained Biased Number Representation for ReRAM-Based Neural Network Accelerators. 15:1-15:17 - Ankit Mondal, Ankur Srivastava:
In Situ Stochastic Training of MTJ Crossbars With Machine Learning Algorithms. 16:1-16:29 - Ramtin Zand, Kerem Yunus Camsari, Supriyo Datta, Ronald F. DeMara:
Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons. 17:1-17:22 - Bingzhe Li, M. Hassan Najafi, David J. Lilja:
Low-Cost Stochastic Hybrid Multiplier for Quantized Neural Networks. 18:1-18:19 - Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu:
A Mixed Signal Architecture for Convolutional Neural Networks. 19:1-19:26 - Praveen K. Pilly, Nigel Stepp, Yannis Liapis, David W. Payton, Narayan Srinivasa:
Hypercolumn Sparsification for Low-Power Convolutional Neural Networks. 20:1-20:16 - Mohsen Imani, Ricardo Garcia, Saransh Gupta, Tajana Rosing:
Hardware-Software Co-design to Accelerate Neural Network Applications. 21:1-21:18 - Maxence Bouvier, Alexandre Valentian, Thomas Mesquida, François Rummens, Marina Reyboz, Elisa Vianello, Edith Beigné:
Spiking Neural Networks Hardware Implementations and Challenges: A Survey. 22:1-22:35
Volume 15, Number 3, June 2019
- Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri:
Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits. 23:1-23:17 - Abdullah M. Zyarah, Dhireesha Kudithipudi:
Neuromemrisitive Architecture of HTM with On-Device Learning and Neurogenesis. 24:1-24:24 - Qixiao Liu, Zhifeng Chen, Zhibin Yu:
MiC: Multi-level Characterization and Optimization of GPGPU Kernels. 25:1-25:24 - Andreas Grimmer, Medina Hamidovic, Werner Haselmayr, Robert Wille:
Advanced Simulation of Droplet Microfluidics. 26:1-26:16 - Yu Liu, Sai Sourabh Yenamachintala, Peng Li:
Energy-efficient FPGA Spiking Neural Accelerators with Supervised and Unsupervised Spike-timing-dependent-Plasticity. 27:1-27:19 - Gaoming Du, Guanyu Liu, Zhenmin Li, Yifan Cao, Duoli Zhang, Yiming Ouyang, Minglun Gao, Zhonghai Lu:
SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method. 28:1-28:26 - Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler:
Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is NP-complete (Research Note). 29:1-29:10 - Sumin Li, Kaixin Huang, Linpeng Huang, Jiashun Zhu:
LiwePMS: A Lightweight Persistent Memory with Wear-aware Memory Management. 30:1-30:24
Volume 15, Number 4, December 2019
- Jae-Sun Seo, Yu Cao, Xin Li, Paul N. Whatmough:
Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2). 31:1-31:2 - Manuel Schmuck, Luca Benini, Abbas Rahimi:
Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory. 32:1-32:25 - Sai Manoj Pudukotai Dinakarrao, Arun Joseph, Anand Haridass, Muhammad Shafique, Jörg Henkel, Houman Homayoun:
Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management. 33:1-33:19 - The H. Vu, Yuichi Okuyama, Abderazek Ben Abdallah:
Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithm and Architecture for 3D-NoC of Spiking Neurons. 34:1-34:28 - Yibin Tang, Ying Wang, Huawei Li, Xiaowei Li:
MV-Net: Toward Real-Time Deep Learning on Mobile GPGPU Systems. 35:1-35:25 - Colin Shea, Tinoosh Mohsenin:
Heterogeneous Scheduling of Deep Neural Networks for Low-power Real-time Designs. 36:1-36:31 - Michaela Blott, Lisa Halder, Miriam Leeser, Linda Doyle:
QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware. 37:1-37:38
- Pampa Howladar, Pranab Roy, Hafizur Rahaman:
A High-performance Homogeneous Droplet Routing Technique for MEDA-based Biochips. 38:1-38:37 - Bing Li, Mengjie Mao, Xiaoxiao Liu, Tao Liu, Zihao Liu, Wujie Wen, Yiran Chen, Hai (Helen) Li:
Thread Batching for High-performance Energy-efficient GPU Memory Design. 39:1-39:21
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