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Integration, Volume 73
Volume 73, July 2020
- Maximilian Neuner, Helmut Graeb:
Verification and revision of the power-down mode for hierarchical analog circuits. 1-9 - Valentin Gutierrez, Gildas Léger:
An adaptive simulation framework for AMS-RF test quality. 10-17 - Adel Hosseiny, Ghassem Jaberipur:
Complex exponential functions: A high-precision hardware realization. 18-29 - Zhiming Zhang, Jaya Dofe, Qiaoyan Yu:
Improving power analysis attack resistance using intrinsic noise in 3D ICs. 30-42 - Ethan Chen, Vanessa Chen:
In-sensor time-domain classifiers using pseudo sigmoid activation functions. 43-49 - Ievgen Kabin, Zoya Dyka, Dan Klann, Peter Langendörfer:
Methods increasing inherent resistance of ECC designs against horizontal attacks. 50-67 - Harpreet Vohra, Ashima Singh, Sukhpal Singh Gill:
An innovative two-stage data compression scheme using adaptive block merging technique. 68-76 - Sayyed Mohammad Razavi, Seyyed Mohammad Razavi:
An efficient and reliable MRF-based methodology for designing low-power VLSI circuits. 77-88 - Ankur Changela, Mazad Zaveri, Deepak Verma:
FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm. 89-100 - Sanjay Vidhyadharan, Surya Shankar Dan, Abhay S. Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad:
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC. 101-113
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