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IEEE Computer Architecture Letters, Volume 10

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Volume 10, Number 1, January - June 2011

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Kevin Skadron:
Editorial: Letter from the Editor-in-Chief. 1-3
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Hans Vandierendonck, André Seznec:
Fairness Metrics for Multi-Threaded Processors. 4-7
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Jie Tang, Shaoshan Liu, Zhimin Gu, Chen Liu, Jean-Luc Gaudiot:
Prefetching in Embedded Mobile Systems Can Be Energy-Efficient. 8-11
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Omer Khan, Mieszko Lis, Yildiz Sinangil, Srinivas Devadas:
DCC: A Dependable Cache Coherence Multicore Architecture. 12-15
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Paul Rosenfeld, Elliott Cooper-Balis, Bruce L. Jacob:
DRAMSim2: A Cycle Accurate Memory System Simulator. 16-19
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Chunyang Gou, Georgi Gaydadjiev:
Exploiting SPMD Horizontal Locality. 20-23
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Xiaoqun Wang, Zhen Ji, Chen Fu, Ming Hu:
GCMS: A Global Contention Management Scheme in Hardware Transactional Memory. 24-27

Volume 10, Number 2, July - December 2011

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Jason Mars, Lingjia Tang, Robert Hundt:
Heterogeneity in "Homogeneous" Warehouse-Scale Computers: A Performance Opportunity. 29-32
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George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally:
Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. 33-36
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Chen-Han Ho, Garret Staus, Aaron Ullmer, Karu Sankaralingam:
Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities. 37-40
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Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato:
Fault-Tolerant Vertical Link Design for Effective 3D Stacking. 41-44
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Inseok Choi, Minshu Zhao, Xu Yang, Donald Yeung:
Experience with Improving Distributed Shared Cache Performance on Tilera's Tile Processor. 45-48
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Pablo Prieto, Valentin Puente, José-Ángel Gregorio:
Multilevel Cache Modeling for Chip-Multiprocessor Systems. 49-52
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Kostas Siozios, Dimitrios Rodopoulos, Dimitrios Soudris:
On Supporting Rapid Thermal Analysis. 53-56

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