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ORCID11th SIES 2016: Krakow, Poland
- 11th IEEE Symposium on Industrial Embedded Systems, SIES 2016, Krakow, Poland, May 23-25, 2016. IEEE 2016, ISBN 978-1-5090-2282-3
- Giulio Corradi:
Keynote at SIES: Heterogeneous processors in SoC simplifies integration of IEC61508 and ISO26262 functional safety designs. The ZYNQ7000 experience. VII-IX
Session 1: Real-Time Control Systems
- Róbinson Medina Sánchez, Sander Stuijk
, Dip Goswami, Twan Basten:
Reconfigurable pipelined sensing for image-based control. 1-8 - Davide Calvaresi, Paolo Sernani, Mauro Marinoni, Andrea Claudi, Alessio Balsini, Aldo Franco Dragoni, Giorgio C. Buttazzo:
A framework based on real-time OS and multi-agents for intelligent autonomous robot competitions. 9-18 - Luca Rizzon, Roberto Passerone:
Cyber/physical co-design in practice: Case studies in metroII. 19-28 - Dániel Darvas, István Majzik, Enrique Blanco Viñuela:
Conformance checking for programmable logic controller programs and specifications. 29-36
Session 2: Mixed-Criticality and Certification
- Amir R. B. Behrouzian, Dip Goswami, Marc Geilen, Martijn Hendriks, Hadi Alizadeh Ara, Eelco P. van Horssen, W. P. M. H. Heemels, Twan Basten:
Sample-drop firmness analysis of TDMA-scheduled control applications. 37-44 - Stephan Schnitzer, Simon Gansel, Frank Dürr, Kurt Rothermel:
Real-time scheduling for 3D GPU rendering. 45-54 - Naim Harb, Carlos Valderrama, Esteban Pelaez, Alexandre Girardi:
FPGA hardware in the loop system for ERTMS-ETCS train equipment testing. 55-62 - Muhammad Ali Awan, Damien Masson, Eduardo Tovar:
Energy efficient mapping of mixed criticality applications on unrelated heterogeneous multicore platforms. 63-72
Session 3: Real-Time Scheduling
- Tomasz Kloda, Bruno d'Ausbourg, Luca Santinelli:
EDF schedulability test for the E-TDL time-triggered framework. 73-82 - Christian Scholer, Rene Krenz-Baath, Ayman Murshed, Roman Obermaisser:
Computing optimal communication schedules for time-triggered networks using an SMT solver. 83-91 - Gianluca Cena, Stefano Scanzio, Lucia Seno, Adriano Valenzano:
A soft real-time scheduling framework for wireless industrial sensor actuator networks. 92-102
Session 4: Automotive Systems
- Leo Hatvani, Reinder J. Bril:
Minimizing stack usage for AUTOSAR/OSEK's restricted fixed-priority preemption threshold support. 103-112 - Martin Lowinski, Dirk Ziegenbein, Sabine Glesner:
Splitting tasks for migrating real-time automotive applications to multi-core ECUs. 113-120 - Sebastian Tobuschat, Rolf Ernst, Arne Hamann, Dirk Ziegenbein:
System-level timing feasibility test for cyber-physical automotive systems. 121-130
Session 5: Probabilistic execution time analysis
- Fabrice Guet, Luca Santinelli, Jérôme Morio:
Probabilistic analysis of cache memories and cache memories impacts on multi-core embedded systems. 131-140 - Pedro Benedicte, Leonidas Kosmidis, Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla:
Modelling the confidence of timing analysis for time randomised caches. 141-148 - Chao Chen, Luca Santinelli, Jérôme Hugues, Giovanni Beltrame:
Static probabilistic timing analysis in presence of faults. 149-158
Work-in-Progress Session
Architectures
- Nicola Bombieri, Federico Busato, Franco Fummi, Michele Scala:
MIPP: A microbenchmark suite for performance, power, and energy consumption characterization of GPU architectures. 159-164 - Maya H. Safieddine, Fadi A. Zaraket, Mohamad Jaber, Rouwaida Kanj, Mazen A. R. Saghir:
Automated FPGA implementations of BIP designs. 165-170 - Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement:
Hardware runtime verification of embedded software in SoPC. 171-176 - Khadija Hadj Salem, Yann Kieffer, Stéphane Mancini:
Efficient algorithms for memory management in embedded vision systems. 177-182
Analysis
- Padma Iyenghar, Arne Noyer, Joachim Engelhardt, Elke Pulvermüller, Clemens Westerkamp:
End-to-end path delay estimation in embedded software involving heterogeneous models. 183-188 - Omair Rafique, Klaus Schneider:
Towards the standardization of plug-and-play devices for model-based designs of embedded systems. 189-192 - Aamir M. Khan, Frédéric Mallet, Muhammad Rashid:
Natural interpretation of UML/MARTE diagrams for system requirements specification. 193-198 - Louis-Marie Givel, Jean-Luc Béchennec, Matthias Brun, Sébastien Faucou, Olivier H. Roux:
Testing real-time embedded software using runtime enforcement. 199-204 - Roberto Medina, Etienne Borde, Laurent Pautet:
Availability analysis for synchronous data-flow graphs in mixed-criticality systems. 205-210 - Dominik Schoenwetter, Alexander Ditter, Dietmar Fey, Ralph Mader:
Improving instruction accurate simulation for parallel automotive applications. 211-214 - Joakim Oscarsson, Max Stolz-Sundnes, Naveen Mohan, Viacheslav Izosimov:
Applying systems-theoretic process analysis in the context of cooperative driving. 215-219
Scheduling
- Dirk Müller:
SS01 - Explicit per-task deadline scaling for uniprocessor scheduling of job-level static mixed-criticality systems. 220-225 - Zhongqi Ma, Ryo Kurachi, Gang Zeng, Hiroaki Takada:
Further analysis on blocking time bounds for partitioned fixed priority multiprocessor scheduling. 226-231 - Zahid Iqbal, Luís Almeida:
Towards an analysis for hierarchies of sporadic servers on Ethernet. 232-237
Use cases
- Robert Brzoza-Woch, Marek Konieczny, Piotr Nawrocki, Tomasz Szydlo, Krzysztof Zielinski:
Embedded systems in the application of fog computing - Levee monitoring use case. 238-243
Session 6: Design for Memory and Shared Resources
- Shreya Adyanthaya, Marc Geilen, Twan Basten, Jeroen Voeten, Ramon R. H. Schiffelers:
Communication aware multiprocessor binding for shared memory systems. 244-253 - Ioannis A. Deligiannis, George Kornaros:
Adaptive memory management scheme for MMU-less embedded systems. 254-261 - Javier Jalle, Mikel Fernández, Jaume Abella, Jan Andersson, Mathieu Patte, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Contention-aware performance monitoring counte support for real-time MPSoCs. 262-271 - Javier Jalle, Eduardo Quiñones, Jaume Abella, Luca Fossati, Marco Zulianello, Francisco J. Cazorla:
Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems. 272-279
Session 7: Real-Time Schedulability Analysis
- Antonio Barros, Patrick Meumeu Yomsi, Luís Miguel Pinho:
Response time analysis of hard real-time tasks sharing software transactional memory data under fully partitioned scheduling. 280-289 - José Carlos Fonseca, Geoffrey Nelissen, Vincent Nélis, Luís Miguel Pinho:
Response time analysis of sporadic DAG tasks under partitioned scheduling. 290-299 - Hadi Alizadeh Ara, Marc Geilen, Twan Basten, Amir R. B. Behrouzian, Martijn Hendriks, Dip Goswami:
Tight temporal bounds for dataflow applications mapped onto shared resources. 300-307
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