default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID17th MTV 2016: Austin, TX, USA
- 17th International Workshop on Microprocessor and SOC Test and Verification, MTV 2016, Austin, TX, USA, December 12-13, 2016. IEEE Computer Society 2016, ISBN 978-1-4673-8924-2
Processor & Memory Verification
- Saddam Jamil Quirem, Prasad Krishna Saravu:
Fake CPU: A Flexible and Simulation Cost-Effective UVC for Testing Shared Caches. 1-6 - Prasad Krishna Saravu:
Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker. 7-14 - Haytham Saafan, M. Watheq El-Kharashi, Ashraf Salem
:
Formal Based Methodology for Inferring Memory Mapped Registers. 15-18 - Senwen Kan, Matthew Lam, Tyler Porter, Jennifer Dworak:
A Case Study: Pre-Silicon SoC RAS Validation for NoC Server Processor. 19-24 - Vibarajan Viswanathan, Juliet Runhaar, Doug Reed, Jun Zhao:
Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging. 25-29 - Ahmed El-Yamany, Sameh El-Ashry, Khaled Salah:
Coverage Closure Efficient UVM Based Generic Verification Architecture for Flash Memory Controllers. 30-34
Security
- Xiaolong Guo, Raj Gautam Dutta, Prabhat Mishra, Yier Jin:
Automatic RTL-to-Formal Code Converter for IP Security Formal Verification. 35-38 - Yang Xie, Chongxi Bao, Yuntao Liu, Ankur Srivastava:
2.5D/3D Integration Technologies for Circuit Obfuscation. 39-44 - Liwei Zhou, Yiorgos Makris:
Hardware-Based Workload Forensics and Malware Detection in Microprocessors. 45-50 - Wei Hu, Alric Althoff, Armita Ardeshiricham, Ryan Kastner:
Towards Property Driven Hardware Security. 51-56
Verification Methodology Innovations
- Khaled Fathy, Khaled Salah:
An Efficient Scenario Based Testing Methodology Using UVM. 57-60 - Amr B. Darwish, Magdy A. El-Moursy, Mohamed Dessouky:
Transaction Level Power Modeling (TLPM) Methodology. 61-64 - Omar Amin, Youssef Ramzy, Omar Ibrahem, Ahmed Fouad, Khaled Mohamed, Mohamed Abdelsalam:
System Verilog Assertions Synthesis Based Compiler. 65-70 - Sainath Karlapalem, Shashank Venugopal:
Scalable, Constrained Random Software Driven Verification. 71-76 - Ahmed El-Yamany:
Echoing the "Generality Concept" through the Bus Functional Model Architecture in Universal Verification Environments. 77-80
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-15 00:25 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
