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ORCID15th MTV 2014: Austin, TX, USA
- 15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014. IEEE Computer Society 2014, ISBN 978-1-4673-6858-2
Session A: Innovation in Best Practices
- Weihua Han:
Improve the Verification Productivity: Some Best Practices from SoC and Processor Projects. 1-3 - Deepak Venkatesan, Pradeep Nagarajan:
A Case Study of Multiprocessor Bugs Found Using RIS Generators and Memory Usage Techniques. 4-9 - Zdenek Prikryl:
Fast Simulation of Pipeline in ASIP Simulators. 10-15 - Michael Mefenza, Franck Yonga, Christophe Bobda:
Automatic UVM Environment Generation for Assertion-Based and Functional Verification of SystemC Designs. 16-21
Session B: It Takes Hardware to Verify Hardware I
- Somnath Banerjee, Tushar Gupta:
Optimized Simulation Acceleration with Partial Testbench Evaluation. 22-27 - Ganesh Venkatakrishnan, Naresh Kumar Kadali:
'Dump What You Need' - A Coverage Methodology to Accelerate SoC Verification. 28-32 - Michele Lora
, Francesco Martinelli, Franco Fummi:
Hardware Synthesis from Software-Oriented UML Descriptions. 33-38
Session C: It Takes Hardware to Verify Hardware II
- Nitin Gupta, Chethan Harakchand:
Embracing the FPGA Challenge for Processor Design Verification. 39-43 - Maneesh Kumar Pandey, Shwetank Shekhar, Amit Sinha, Arun Mishra:
An FPGA Based Ecosystem for USBPHY Validation. 44-48
Session D: Mutation Analysis and Assertions
- Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey:
Mutation Based Feature Localization. 49-54 - Moaz Mostafa, Mona Safar, M. Watheq El-Kharashi, Mohamed Dessouky:
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation. 55-60 - Mohamed O. Kayed, Mohamed Abdelsalam, Rafik Guindi:
A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML. 61-66 - Mrugesh Walimbe:
JTAG-AXI Debug IP with Performance Meter Mode. 67-69
Session E: Special Session on Triage and Debug
- Daniel Hansson:
Continuous Linting with Automatic Debug. 70-72
Session F: Stimulus Generation - A Smart Slot Machine
- Shajid Thiruvathodi, Deepak Yeggina:
A Random Instruction Sequence Generator for ARM Based Systems. 73-77 - Peter-Michael Seidel:
Directed Test Case Generation for x86 Instruction Decoding. 78-82
Session G: Formal Magic
- Lukás Charvát, Ales Smrcka, Tomás Vojnar:
Using Formal Verification of Parameterized Systems in RAW Hazard Analysis in Microprocessors. 83-89 - Peter-Michael Seidel:
A Case for Multi-level Combination of Theorem Proving and Model Checking Tools. 90-97
Session H: Innovative Memory Verification
- John Hudson, Gunaranjan Kurucheti:
A Configurable Random Instruction Sequence (RIS) Tool for Memory Coherence in Multi-processor Systems. 98-101 - Parikshit Pritam Dhodapkar:
Synthesizable Memory Models for Virtual Prototyping. 102-104 - Andrea Höller, Gerhard Schonfelder, Nermin Kajtazovic, Tobias Rauter, Christian Kreiner:
FIES: A Fault Injection Framework for the Evaluation of Self-Tests for COTS-Based Safety-Critical Systems. 105-110
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