Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHLDVT 2017: Santa Cruz, CA, USA
- 2017 IEEE International High Level Design Validation and Test Workshop, HLDVT 2017, Santa Cruz, CA, USA, October 5-6, 2017. IEEE Computer Society 2017, ISBN 978-1-5090-3997-5
Session 1: Testing and Verification
- Guy Barash, Eitan Farchi:
A randomized algorithm for constructing cross-feature tests from single feature tests. 1-8 - Tonmoy Roy, Michael Hsiao:
Reachability analysis in RTL circuits using k-induction bounded model checking. 9-16 - Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi:
A novel SAT-based ATPG approach for transition delay faults. 17-22
Session 2: Modeling and Validation
- Michele Lora:
Validation of HMI applications for industrial smart display. 23-30 - Maral Amir, Tony Givargis:
HES machine: Harmonic equivalent state machine modeling for cyber-physical systems. 31-38 - Sophia Balkovski, Ian G. Harris:
Designing cyber-physical systems from natural language descriptions. 39-44
Session 3: Post-silicon Validation and 3D design
- Pankaj Moharikar, Jayakrishna Guddeti:
Automated test generation for post silicon microcontroller validation. 45-52 - Siroos Madani, Kasem Khalil
, Bappaditya Dey, Devante Bonton, Magdy A. Bayoumi:
Repair techniques for aged TSVs in 3D integrated circuits. 53-58 - Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
RTL level trace signal selection and coverage estimation during post-silicon validation. 59-66
Session 4: Applied Design and Verification Techniques
- Florenc Demrozi, Riccardo Zucchelli, Graziano Pravadelli:
Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTL. 67-73 - Zhongqi Cheng, Tim Schmidt, Guantao Liu, Rainer Dömer:
Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case study. 74-81 - Daniela De Venuto, Giovanni Mezzina, V. L. Gallo:
Design and implementation of FPGA-based muscle conduction velocity tracker in dynamic contractions during the gait. 82-86
WIP Session
- Zahra Shirmohammadi, Hadi Zamani Sabzi, Seyed Ghassem Miremadi:
3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs. 87-90 - Masahiro Fujita:
An approach to approximate computing: Logic transformations for one-minterm changes in specification. 91-94 - Keerthikumara Devarajegowda, Wolfgang Ecker:
On generation of properties from specification. 95-98
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-06-10 21:35 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
