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ORCIDCODES+ISSS 2019: New York, NY, USA
- Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, CODES+ISSS 2019, part of ESWEEK 2019, New York, NY, USA, October 13-18, 2019. ACM 2019, ISBN 978-1-4503-6923-7
- Jeonggyu Jang
, Kyusik Choi, Hoeseok Yang:
A SIMD-aware pruning technique for convolutional neural networks with multi-sparsity levels: work-in-progress. 1:1-1:2 - Kyungchul Park, Youngmin Yi:
BPNet: Branch-pruned conditional neural network for systematic time-accuracy tradeoff in DNN inference: work-in-progress. 2:1-2:2 - Samet E. Arda, Anish Krishnakumar, A. Alper Goksoy, Joshua Mack, Nirmal Kumbhare, Anderson L. Sartor, Ali Akoglu, Radu Marculescu, Ümit Y. Ogras:
A simulation framework for domain-specific system-on-chips: work-in-progress. 3:1-3:2 - Arko Dutt, Govind Narasimman, Lin Jie, Vijay Ramaseshan Chandrasekhar, Mohamed M. Sabry:
EAST-DNN: Expediting architectural SimulaTions using deep neural networks: work-in-progress. 4:1-4:2 - Hideki Takase, Kentaro Matsui, Yoshihiro Ueno, Masakazu Mori, Yuki Hisae, Susumu Yamazaki:
A concept of a hardware design environment with the functional language elixir: work-in-progress. 5:1-5:2 - Supreeth Mysore Shivanandamurthy, Ishan G. Thakkar, Sayed Ahmad Salehi:
A scalable stochastic number generator for phase change memory based in-memory stochastic processing: work-in-progress. 6:1-6:2 - Dongning Ma, Siyu Shen, Xun Jiao:
DeVos: A learning-based delay model of voltage-scaled circuits: work-in-progress. 7:1-7:2 - Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
Mitigating inter-channel crosstalk non-uniformity in microring filter arrays of photonic NoCs: work-in-progress. 8:1-8:2 - Yajuan Du, Wei Liu, Rui Wang, Yao Zhou, Jason Xue:
PreGC: Pre-migrating valid pages to relieve performance cliff of 3D solid-state drives: work-in-progress. 9:1-9:2 - Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis:
Design space exploration of multi-task processing on space shared FPGAs: work-in-progress. 10:1-10:2 - Ruben Vazquez, Ann Gordon-Ross, Greg Stitt:
Offloading cache configuration prediction to an FPGA for hardware speedup and overhead reduction: work-in-progress. 11:1-11:2 - Rajesh Kedia, M. Balakrishnan, Kolin Paul:
A case for design space exploration of context-aware adaptive embedded systems: work-in-progress. 12:1-12:2 - Yang Yang, Chao Wang, Xuehai Zhou:
Drama: A high efficient neural network accelerator on FPGA using dynamic reconfiguration: work-in-progress. 13:1-13:2 - Jiashen Cao, Ramyad Hadidi, Joy Arulraj, Hyesoon Kim:
Video analytics from edge to server: work-in-progress. 14:1-14:2 - Yawen Wu, Zhenge Jia, Fei Fang, Jingtong Hu:
Cooperative communication between two transiently powered sensors by reinforcement learning: work-in-progress. 15:1-15:2 - Zhenge Jia, Yawen Wu, Jingtong Hu:
Q-learning based routing for transiently powered wireless sensor network: work-in-progress. 16:1-16:2 - Alessio Burrello, Francesco Conti, Angelo Garofalo, Davide Rossi, Luca Benini:
DORY: Lightweight memory hierarchy management for deep NN inference on IoT endnodes: work-in-progress. 17:1-17:2 - Erman Nghonda Tchinda, Danielle Tchuinkou Kwadjo, Christophe Bobda:
A distributed smart camera apparatus to enable scene immersion: work-in-progress. 18:1-18:2 - Jinyu Zhan, Ying Li, Wei Jiang, Junting Wu, Jianping Zhu:
An improved network interface card with query filter for big data systems: work-in-progress. 19:1-19:2 - Eberle A. Rambo, Thawra Kadeed, Rolf Ernst, Minjun Seo, Fadi J. Kurdahi, Bryan Donyanavard, Caio Batista de Melo, Biswadip Maity, Kasra Moazzemi, Kenneth Michael Stewart, Saehanseul Yi, Amir M. Rahmani, Nikil D. Dutt, Florian Maurer, Nguyen Anh Vu Doan, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf:
The information processing factory: a paradigm for life cycle management of dependable systems. 20:1-20:2 - Paul Bogdan, Fan Chen, Aryan Deshwal, Janardhan Rao Doppa, Biresh Kumar Joardar, Hai (Helen) Li, Shahin Nazarian, Linghao Song, Yao Xiao:
Taming extreme heterogeneity via machine learning based design of autonomous manycore systems. 21:1-21:10
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