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ORCIDAsianHOST 2024: Kobe, Japan
- Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2024, Kobe, Japan, December 16-18, 2024. IEEE 2024, ISBN 979-8-3503-6806-2
- Kazuki Monta, Takafumi Oki, Rikuu Hasegawa, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Norman Chang:
A Hybrid Simulation Approach for Accurate and Fast System-Level Side-Channel Leakage Evaluation. 1-6 - Anurag Kamal, Vishesh Mishra, Sparsh Mittal, Mahendra Rathor, Chandan Kumar, Urbi Chatterjee:
Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF. 1-6 - Zeru Lan, Chunlu Wang, Pengfei Qiu, Yu Jin, Yihao Yang, Dongsheng Wang, Gang Qu:
AutoGuard: A Secure Implementation of the Conditional Branch Instruction. 1-6 - Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham:
A True Random Number Generator on FPGA with Jitter-Sampling by Ring Generator. 1-6 - Haruka Hirata, Yusaku Harada, Yuko Hara, Kazuo Sakiyama, Yang Li:
Yet Another Physical Leakage Assessment with the Wasserstein Distance. 1-6 - Meriem Mahar, Maamar Ouladj, Sylvain Guilley, Hacène Belbachir, Farid Mokrane:
Exact Template Attacks with Spectral Computation. 1-6 - Jiongzhe Su, Haoran Du, Quanhai Zhu, Mingtao Chen, Keyang Zhang, Bo Liu, Hao Cai:
Unveiling Security MRAM-OTP Macro using MTJ Hard Breakdown Mechanism. 1-6 - You Wang, Chaoyue Zhang, Yefan Xu, Yu Gong, Hao Cai, Weiqiang Liu:
Truly Random Number Generation by Using in-Plane Magnetic Tunnel Junction with Weak Anisotropy. 1-5 - James Moore, Jack Miskelly, Máire O'Neill, Chongyan Gu:
A Novel FPGA Mutually Coupled Configurable Ring Oscillator PUF. 1-6 - Tomosuke Ichioka, Yohei Watanabe, Yuko Hara:
PreLock: Precision Locking for Protecting Embedded Processor. 1-6 - Bowen Hu, Weiyang He, Kuo Wang, Chip-Hong Chang:
A Black-Box Targeted Misclassification Attack on Edge AI with Adversarial Examples Generated from RAW Image Sensor Data. 1-6 - Luke Beckwith, Huizhen Zhou, Jens-Peter Kaps, Kris Gaj:
Power Side-Channel Key Recovery Attack on a Hardware Implementation of BIKE. 1-6 - Wen Wang, Peng Liu:
A Consistency Testing Method for Revealing RISC-V Processor's Undocumented Instructions. 1-6 - Raphaël Comps, Jean-Baptiste Rigaud, Jean-Max Dutertre:
Analysis and Mitigation of Hybrid CMOS/MRAM DFF Vulnerabilities to Laser Fault Injection. 1-6 - Xinyuan Zhao, Yijun Cui, Fei Lyu, Chongyan Gu, Chenghua Wang, Weiqiang Liu:
High Reliable Processor-Based PUF on Voltage Over-Scaling Technique. 1-6 - Maoyuan Cai, Aijiao Cui, Yier Jin:
SecRiSBen: A RISC-V based SoC Benchmark for Evaluation of Security Verification Tools. 1-6 - Ville Yli-Mäyry, Thomas Perianin, Sylvain Guilley:
Automated Search of Instructions Vulnerable to Fault Injection Attacks in Command Authorization Checks of a TPM 2.0 Implementation. 1-6
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