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8. IEEE INTERACT 2004: Madrid, Spain
- 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 15 February 2004, Madrid, Spain. IEEE Computer Society 2004, ISBN 0-7695-2061-8
Loop Optimization
- Youfeng Wu, Maurício Breternitz Jr.
, Tevi Devor:
Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary Translato. 3-12 - Jan Müller, Dirk Fimmel, Renate Merker:
Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. 13-21
Garbage Collection
- José Manuel Velasco, David Atienza, Francky Catthoor, Francisco Tirado
, Katzalin Olcoz
, Jose Manuel Mendias:
Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems. 25-32 - José Manuel Velasco
, Antonio Ortiz, Katzalin Olcoz
, Francisco Tirado
:
Dynamic Management of Nursery Space Organization in Generational Collection. 33-40
Energy Efficient Computing
- Osman S. Unsal
, Israel Koren, C. Mani Krishna, Csaba Andras Moritz:
Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction. 43-52 - Gilles Pokam, François Bodin:
Energy-Efficiency Potential of a Phase-Based Cache Resizing Scheme for Embedded Systems. 53-62
Fast Simulation and I-Cache
- Peter K. Szwed, Daniel Marques, Robert M. Buels, Sally A. McKee, Martin Schulz
:
SimSnap: Fast-Forwarding via Native Execution and Application-Level Checkpointing. 65-74 - Ravi V. Batchu, Daniel A. Jiménez:
Exploiting Procedure Level Locality to Reduce Instruction Cache Misses. 75-84
Branch Optimizations
- Manel Fernández, Roger Espasa:
Link-Time Optimization Techniques for Eliminating Conditional Branch Redundancies. 87-96 - Oliverio J. Santana
, Alex Ramírez, Mateo Valero
:
Reducing Fetch Architecture Complexity Using Procedure Inlining. 97-106
Data Cache Performance Optimization
- Evangelia Athanasaki, Nectarios Koziris:
Fast Indexing for Blocked Array Layouts to Improve Multi-Level Cache Locality. 109-119 - Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
:
Data Movement Optimization for Software-Controlled On-Chip Memory. 120-127

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