- Frank E. B. Ophelders, Marco Bekooij, Henk Corporaal:
A tuneable software cache coherence protocol for heterogeneous MPSoCs. CODES+ISSS 2009: 383-392 - Daniel Christopher Powell, Björn Franke
:
Using continuous statistical machine learning to enable high-speed performance prediction in hybrid instruction-/cycle-accurate instruction set simulators. CODES+ISSS 2009: 315-324 - Yue Qian, Zhonghai Lu, Wenhua Dou:
Applying network calculus for performance analysis of self-similar traffic in on-chip networks. CODES+ISSS 2009: 453-460 - Meikang Qiu, Lei Zhang, Edwin Hsing-Mean Sha:
ILP optimal scheduling for multi-module memory. CODES+ISSS 2009: 277-286 - Praveen Raghavan, Francky Catthoor:
SARA: StreAm register allocation. CODES+ISSS 2009: 41-50 - Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto:
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. CODES+ISSS 2009: 325-334 - Jonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner:
Memory-efficient distribution of regular expressions for fast deep packet inspection. CODES+ISSS 2009: 147-154 - Björn Sander, Jürgen Schnerr, Oliver Bringmann:
ESL power analysis of embedded processors for temperature and reliability estimations. CODES+ISSS 2009: 239-248 - Simon Schliecker, Rolf Ernst:
A recursive approach to end-to-end path latency computation in heterogeneous multiprocessor systems. CODES+ISSS 2009: 433-442 - Christian Schröder, Wolfgang Klingauf, Robert Günzel, Mark Burton, Eric Roesler:
Configuration and control of SystemC models using TLM middleware. CODES+ISSS 2009: 81-88 - Daniel Schwartz-Narbonne, Carven Chan, Yogesh S. Mahajan, Sharad Malik:
Supporting RTL flow compatibility in a microarchitecture-level design framework. CODES+ISSS 2009: 343-352 - Scott Sirowy, Bailey Miller, Frank Vahid:
Portable SystemC-on-a-chip. CODES+ISSS 2009: 21-30 - Matthias Bo Stuart, Mikkel Bystrup Stensgaard, Jens Sparsø:
Synthesis of topology configurations and deadlock free routing algorithms for ReNoC-based systems-on-chip. CODES+ISSS 2009: 481-490 - David Szczesny, Sebastian Hessel, Felix Bruns, Attila Bilgic:
On-the-fly hardware acceleration for protocol stack processing in next generation mobile devices. CODES+ISSS 2009: 155-162 - Leonel Tedesco, Fabien Clermidy, Fernando Moraes:
A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures. CODES+ISSS 2009: 109-118 - Anders Sejer Tranberg-Hansen, Jan Madsen:
A compositional modelling framework for exploring MPSoC systems. CODES+ISSS 2009: 1-10 - Antonino Tumeo, Marco Branca, Lorenzo Camerini, Christian Pilato, Pier Luca Lanzi, Fabrizio Ferrandi, Donatella Sciuto:
Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach. CODES+ISSS 2009: 443-452 - Alexander Viehl, Michael Pressler, Oliver Bringmann:
Bottom-up performance analysis considering time slice based software scheduling at system level. CODES+ISSS 2009: 423-432 - Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo:
Energy-efficiency for multiframe real-time tasks on a dynamic voltage scaling processor. CODES+ISSS 2009: 211-220 - Chengmo Yang, Mingjing Chen, Alex Orailoglu:
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses. CODES+ISSS 2009: 249-256 - Wolfgang Rosenstiel, Kazutoshi Wakabayashi:
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009. ACM 2009, ISBN 978-1-60558-628-1 [contents]
