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@article{DBLP:journals/vlsisp/Ahmed-OuameurM07,
  author       = {Messaoud Ahmed Ouameur and
                  Daniel Massicotte},
  title        = {Real-time {DSP} and {FPGA} Implementation of Wiener {LMS} Based Multipath
                  Channel Estimation in 3G {CDMA} Systems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {3},
  pages        = {259--279},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-007-0051-z},
  doi          = {10.1007/S11265-007-0051-Z},
  timestamp    = {Thu, 07 Mar 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Ahmed-OuameurM07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/Arnold07,
  author       = {Jeffrey M. Arnold},
  title        = {The Architecture and Development Flow of the {S5} Software Configurable
                  Processor},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {1},
  pages        = {3--14},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0012-y},
  doi          = {10.1007/S11265-006-0012-Y},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/Arnold07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BrebnerCW07,
  author       = {Gordon J. Brebner and
                  Samarjit Chakraborty and
                  Weng{-}Fai Wong},
  title        = {Editorial for the Special Issue on Field Programmable Technology},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {1},
  pages        = {1--2},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0035-4},
  doi          = {10.1007/S11265-006-0035-4},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BrebnerCW07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChengS07,
  author       = {Albert Mo Kim Cheng and
                  Feng Shang},
  title        = {Priority-driven Coding and Transmission of Progressive {JPEG} Images
                  for Real-Time Applications},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {2},
  pages        = {169--182},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0044-3},
  doi          = {10.1007/S11265-006-0044-3},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChengS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChengZ07,
  author       = {Albert M. K. Cheng and
                  Zhubin Zhang},
  title        = {Improving Web Server Performance with Adaptive Proxy Caching in Soft
                  Real-time Mobile Applications},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {2},
  pages        = {103--115},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0021-x},
  doi          = {10.1007/S11265-006-0021-X},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChengZ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/CoutinhoJWLLMY07,
  author       = {Jos{\'{e}} Gabriel F. Coutinho and
                  M. P. T. Juvonen and
                  J. L. Wang and
                  Benny Lo and
                  Wayne Luk and
                  Oskar Mencer and
                  Guang{-}Zhong Yang},
  title        = {Designing a Posture Analysis System with Hardware Implementation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {1},
  pages        = {33--45},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0016-7},
  doi          = {10.1007/S11265-006-0016-7},
  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/CoutinhoJWLLMY07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/HanHCCP07,
  author       = {Wei Han and
                  Kwok{-}Wai Hon and
                  Cheong{-}Fat Chan and
                  Oliver Chiu{-}sing Choy and
                  Kong{-}Pang Pun},
  title        = {A Speech Recognition {IC} Using Hidden Markov Models with Continuous
                  Observation Densities},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {3},
  pages        = {223--232},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-007-0049-6},
  doi          = {10.1007/S11265-007-0049-6},
  timestamp    = {Mon, 04 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/HanHCCP07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/JeongK07,
  author       = {H. Jeong and
                  Y. Kim},
  title        = {A Systolic Architecture and Implementation of Feedback Network for
                  Blind Source Separation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {2},
  pages        = {117--126},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0036-3},
  doi          = {10.1007/S11265-006-0036-3},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/JeongK07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/JuliatoALD07,
  author       = {Marcio Juliato and
                  Guido Araujo and
                  Julio C{\'{e}}sar L{\'{o}}pez{-}Hern{\'{a}}ndez and
                  Ricardo Dahab},
  title        = {A Custom Instruction Approach for Hardware and Software Implementations
                  of Finite Field Arithmetic over F\({}_{\mbox{2\({}^{\mbox{163}}\)}}\)
                  using Gaussian Normal Bases},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {1},
  pages        = {59--76},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0015-8},
  doi          = {10.1007/S11265-006-0015-8},
  timestamp    = {Wed, 12 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/JuliatoALD07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KinaneO07,
  author       = {Andrew Kinane and
                  Noel E. O'Connor},
  title        = {Energy-efficient Hardware Accelerators for the {SA-DCT} and Its Inverse},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {2},
  pages        = {127--152},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0022-9},
  doi          = {10.1007/S11265-006-0022-9},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KinaneO07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KordasiewiczS07,
  author       = {Roman C. Kordasiewicz and
                  Shahram Shirani},
  title        = {On Hardware Implementations Of {DCT} and Quantization Blocks for {H.264/AVC}},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {2},
  pages        = {93--102},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0030-9},
  doi          = {10.1007/S11265-006-0030-9},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KordasiewiczS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KordasiewiczS07a,
  author       = {Roman C. Kordasiewicz and
                  Shahram Shirani},
  title        = {On Hardware Implementations Of {DCT} and Quantization Blocks for {H.264/AVC}},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {3},
  pages        = {189--199},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0043-4},
  doi          = {10.1007/S11265-006-0043-4},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KordasiewiczS07a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LeeC07,
  author       = {Yi{-}Hsuan Lee and
                  Cheng Chen},
  title        = {An Efficient Code Generation Algorithm for Non-orthogonal {DSP} Architecture},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {3},
  pages        = {281--296},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-007-0053-x},
  doi          = {10.1007/S11265-007-0053-X},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LeeC07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LeeL07,
  author       = {Sze Wei Lee and
                  Soon{-}Chieh Lim},
  title        = {An Enhanced Memory Address Mapping Scheme for Improved Memory Access
                  Performance of 2-D {DWT} Processing Systems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {3},
  pages        = {201--221},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0042-5},
  doi          = {10.1007/S11265-006-0042-5},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LeeL07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MajerTAB07,
  author       = {Mateusz Majer and
                  J{\"{u}}rgen Teich and
                  Ali Ahmadinia and
                  Christophe Bobda},
  title        = {The Erlangen Slot Machine: {A} Dynamically Reconfigurable FPGA-based
                  Computer},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {1},
  pages        = {15--31},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0017-6},
  doi          = {10.1007/S11265-006-0017-6},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MajerTAB07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MbayeBSP07,
  author       = {Mame Maria Mbaye and
                  Normand B{\'{e}}langer and
                  Yvon Savaria and
                  Samuel Pierre},
  title        = {A Novel Application-specific Instruction-set Processor Design Approach
                  for Video Processing Acceleration},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {3},
  pages        = {297--315},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-007-0050-0},
  doi          = {10.1007/S11265-007-0050-0},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MbayeBSP07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/McLooneM07,
  author       = {M{\'{a}}ire McLoone and
                  Ciaran McIvor},
  title        = {High-speed {\&} Low Area Hardware Architectures of the Whirlpool
                  Hash Function},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {1},
  pages        = {47--57},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0013-x},
  doi          = {10.1007/S11265-006-0013-X},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/McLooneM07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MunCH07,
  author       = {Jun{-}Hee Mun and
                  Shung Han Cho and
                  Sangjin Hong},
  title        = {Flexible Controller Design and Its Application for Concurrent Execution
                  of Buffer Centric Dataflows},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {3},
  pages        = {233--257},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0041-6},
  doi          = {10.1007/S11265-006-0041-6},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MunCH07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SansaloniPTV07,
  author       = {T. Sansaloni and
                  A. Perez{-}Pascual and
                  Vicente Torres{-}Carot and
                  Javier Valls},
  title        = {Scheme for Reducing the Storage Requirements of {FFT} Twiddle Factors
                  on FPGAs},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {2},
  pages        = {183--187},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-007-0055-8},
  doi          = {10.1007/S11265-007-0055-8},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SansaloniPTV07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ThomasL07,
  author       = {David B. Thomas and
                  Wayne Luk},
  title        = {High Quality Uniform Random Number Generation Using {LUT} Optimised
                  State-transition Matrices},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {1},
  pages        = {77--92},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0014-9},
  doi          = {10.1007/S11265-006-0014-9},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ThomasL07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/XueSS07,
  author       = {Chun Xue and
                  Zili Shao and
                  Edwin Hsing{-}Mean Sha},
  title        = {Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {47},
  number       = {2},
  pages        = {153--167},
  year         = {2007},
  url          = {https://doi.org/10.1007/s11265-006-0034-5},
  doi          = {10.1007/S11265-006-0034-5},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/XueSS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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