Search dblp for Publications

export results for "toc:db/journals/vlsisp/vlsisp19.bht:"

 download as .bib file

@article{DBLP:journals/vlsisp/AckenIO98,
  author       = {Kevin P. Acken and
                  Mary Jane Irwin and
                  Robert Michael Owens},
  title        = {A Parallel {ASIC} Architecture for Efficient Fractal Image Coding},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {97--113},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008005616596},
  doi          = {10.1023/A:1008005616596},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/AckenIO98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BajardDM98,
  author       = {Jean{-}Claude Bajard and
                  Laurent{-}St{\'{e}}phane Didier and
                  Jean{-}Michel Muller},
  title        = {A New Euclidean Division Algorithm for Residue Number Systems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {167--178},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008065819322},
  doi          = {10.1023/A:1008065819322},
  timestamp    = {Sun, 04 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BajardDM98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BernsN98,
  author       = {Jan Peter Berns and
                  Tobias G. Noll},
  title        = {A Flexible 200 {GOPS} {HDTV} Motion Estimation Chip},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {85--95},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008053532525},
  doi          = {10.1023/A:1008053532525},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BernsN98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BroggiCGSPR98,
  author       = {Alberto Broggi and
                  Gianni Conte and
                  Francesco Gregoretti and
                  Claudio Sanso{\`{e}} and
                  Roberto Passerone and
                  Leonardo Maria Reyneri},
  title        = {Design and Implementation of the {PAPRICA} Parallel Architecture},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {1},
  pages        = {5--18},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008095714465},
  doi          = {10.1023/A:1008095714465},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BroggiCGSPR98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChangWP98,
  author       = {Yun{-}Nan Chang and
                  Ching{-}Yi Wang and
                  Keshab K. Parhi},
  title        = {Heuristic Loop-Based Scheduling and Allocation for {DSP} Synthesis
                  with Heterogeneous Functional Units},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {3},
  pages        = {243--256},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008017808032},
  doi          = {10.1023/A:1008017808032},
  timestamp    = {Sun, 04 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChangWP98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChenK98,
  author       = {Yen{-}Kuang Chen and
                  Sun{-}Yuan Kung},
  title        = {A Systolic Design Methodology with Application to Full-Search Block-Matching
                  Architectures},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {1},
  pages        = {51--77},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008012332212},
  doi          = {10.1023/A:1008012332212},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChenK98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ClaussL98,
  author       = {Philippe Clauss and
                  Vincent Loechner},
  title        = {Parametric Analysis of Polyhedral Iteration Spaces},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {179--194},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008069920230},
  doi          = {10.1023/A:1008069920230},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ClaussL98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/HirschbergDKSH98,
  author       = {Jeffrey D. Hirschberg and
                  David M. Dahle and
                  Kevin Karplus and
                  Don Speck and
                  Richard Hughey},
  title        = {Kestrel: {A} Programmable Array for Sequence Analysis},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {115--126},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008057617504},
  doi          = {10.1023/A:1008057617504},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/HirschbergDKSH98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LeeF98,
  author       = {Hyuk{-}Jae Lee and
                  Jos{\'{e}} A. B. Fortes},
  title        = {Automatic Generation of Modular Time-Space Mappings and Data Alignments},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {195--208},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008074021139},
  doi          = {10.1023/A:1008074021139},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LeeF98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/LiuLCL98,
  author       = {J. G. Liu and
                  Hon Fung Li and
                  Francis H. Y. Chan and
                  Francis K. Lam},
  title        = {Fast Discrete Cosine Transform via Computation of Moments},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {3},
  pages        = {257--268},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008021924871},
  doi          = {10.1023/A:1008021924871},
  timestamp    = {Wed, 02 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/LiuLCL98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/OwensV98,
  author       = {Robert Michael Owens and
                  Mohan Vishwanath},
  title        = {A Very Efficient Storage Structure for {DWT} and {IDWT} Filters},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {3},
  pages        = {215--225},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008088906215},
  doi          = {10.1023/A:1008088906215},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/OwensV98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ParhiT98,
  author       = {Keshab K. Parhi and
                  Valerie E. Taylor},
  title        = {Guest Editors' Introduction},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {83},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008001515687},
  doi          = {10.1023/A:1008001515687},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ParhiT98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ParkKL98,
  author       = {Chaeryung Park and
                  Taewhan Kim and
                  C. L. Liu},
  title        = {Register Allocation - {A} Hierarchical Reduction Approach},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {3},
  pages        = {269--285},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008073925779},
  doi          = {10.1023/A:1008073925779},
  timestamp    = {Sat, 14 Dec 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ParkKL98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/VillalbaLZ98,
  author       = {Julio Villalba and
                  Tom{\'{a}}s Lang and
                  Emilio L. Zapata},
  title        = {Parallel Compensation of Scale Factor for the {CORDIC} Algorithm},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {3},
  pages        = {227--241},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008013707124},
  doi          = {10.1023/A:1008013707124},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/VillalbaLZ98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/VillalbaZAB98,
  author       = {Julio Villalba and
                  Emilio L. Zapata and
                  Elisardo Antelo and
                  Javier D. Bruguera},
  title        = {Radix-4 Vectoring {CORDIC} Algorithm and Architectures},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {2},
  pages        = {127--147},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008061701575},
  doi          = {10.1023/A:1008061701575},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/VillalbaZAB98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/YouL98,
  author       = {Jaehee You and
                  Sang Uk Lee},
  title        = {High Throughput, Scalable {VLSI} Architecture for Block Matching Motion
                  Estimation},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {1},
  pages        = {39--50},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008060215374},
  doi          = {10.1023/A:1008060215374},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/YouL98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ZimmermannA98,
  author       = {Karl{-}Heinz Zimmermann and
                  Wolfgang Achtziger},
  title        = {On Time Optimal Implementation of Uniform Recurrences onto Array Processors
                  via Quadratic Programming},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {19},
  number       = {1},
  pages        = {19--38},
  year         = {1998},
  url          = {https://doi.org/10.1023/A:1008008231304},
  doi          = {10.1023/A:1008008231304},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ZimmermannA98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.