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@article{DBLP:journals/vlsi/AizikK11,
  author       = {Yoni Aizik and
                  Avinoam Kolodny},
  title        = {Finding the Energy Efficient Curve: Gate Sizing for Minimum Power
                  under Delay Constraints},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {845957:1--845957:13},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/845957},
  doi          = {10.1155/2011/845957},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/AizikK11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChaudhryASH11,
  author       = {Mohammad Asad R. Chaudhry and
                  Zakia Asad and
                  Alexander Sprintson and
                  Jiang Hu},
  title        = {Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees
                  and Network Coding Topologies},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {892310:1--892310:9},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/892310},
  doi          = {10.1155/2011/892310},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChaudhryASH11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/DharPR11,
  author       = {Subhra Dhar and
                  Manisha Pattanaik and
                  Poolla Rajaram},
  title        = {Advancement in Nanoscale {CMOS} Device Design En Route to Ultra-Low-Power
                  Applications},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {178516:1--178516:19},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/178516},
  doi          = {10.1155/2011/178516},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/DharPR11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/HeDBG11,
  author       = {Ou He and
                  Sheqin Dong and
                  Jinian Bian and
                  Satoshi Goto},
  title        = {Buffer Planning for {IP} Placement Using Sliced-LFF},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {530851:1--530851:10},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/530851},
  doi          = {10.1155/2011/530851},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/HeDBG11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Hu0D11,
  author       = {Shiyan Hu and
                  Zhuo Li and
                  Yangdong Deng},
  title        = {{CAD} for Gigascale SoC Design and Verification Solutions},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {398390:1--398390:2},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/398390},
  doi          = {10.1155/2011/398390},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Hu0D11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KanjJN11,
  author       = {Rouwaida Kanj and
                  Rajiv V. Joshi and
                  Sani R. Nassif},
  title        = {The Impact of Statistical Leakage Models on Design Yield Estimation},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {471903:1--471903:12},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/471903},
  doi          = {10.1155/2011/471903},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/KanjJN11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KhanW11,
  author       = {Tareq Hasan Khan and
                  Khan A. Wahid},
  title        = {Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {343787:1--343787:12},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/343787},
  doi          = {10.1155/2011/343787},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/KhanW11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/LeeM11,
  author       = {Dongjin Lee and
                  Igor L. Markov},
  title        = {{CONTANGO:} Integrated Optimization of SoC Clock Networks},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {407507:1--407507:12},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/407507},
  doi          = {10.1155/2011/407507},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/LeeM11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MehtaDD11,
  author       = {Usha Sandeep Mehta and
                  Kankar S. Dasgupta and
                  Niranjan M. Devashrayee},
  title        = {Suitability of Various Low-Power Testing Techniques for {IP} Core-Based
                  SoC: {A} Survey},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {948926:1--948926:7},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/948926},
  doi          = {10.1155/2011/948926},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/MehtaDD11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MehtaDD11a,
  author       = {Usha Sandeep Mehta and
                  Kankar S. Dasgupta and
                  Nirnjan M. Devashrayee},
  title        = {Weighted Transition Based Reordering, Columnwise Bit Filling, and
                  Difference Vector: {A} Power-Aware Test Data Compression Method},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {756561:1--756561:8},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/756561},
  doi          = {10.1155/2011/756561},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/MehtaDD11a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/PanditMP11,
  author       = {Soumya Pandit and
                  Chittaranjan A. Mandal and
                  Amit Patra},
  title        = {A Methodology for Generation of Performance Models for the Sizing
                  of Analog High-Level Topologies},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {475952:1--475952:17},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/475952},
  doi          = {10.1155/2011/475952},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/PanditMP11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RiceMA11,
  author       = {Jacqueline E. Rice and
                  Jon C. Muzio and
                  Neil Anderson},
  title        = {New Considerations for Spectral Classification of Boolean Switching
                  Functions},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {356137:1--356137:9},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/356137},
  doi          = {10.1155/2011/356137},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/RiceMA11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SahaS11,
  author       = {Debasri Saha and
                  Susmita Sur{-}Kolay},
  title        = {SoC: {A} Real Platform for {IP} Reuse, {IP} Infringement, and {IP}
                  Protection},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {731957:1--731957:10},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/731957},
  doi          = {10.1155/2011/731957},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/SahaS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ShanavasG11,
  author       = {I. Hameem Shanavas and
                  Ramaswamy Kannan Gnanamurthy},
  title        = {Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary
                  Algorithms},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {896241:1--896241:9},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/896241},
  doi          = {10.1155/2011/896241},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ShanavasG11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SunXWWTDC11,
  author       = {Guanyi Sun and
                  Shengnan Xu and
                  Xu Wang and
                  Dawei Wang and
                  Eugene Tang and
                  Yangdong Deng and
                  Sun Chan},
  title        = {A High-Throughput, High-Accuracy System-Level Simulation Framework
                  for System on Chips},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {726014:1--726014:17},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/726014},
  doi          = {10.1155/2011/726014},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/SunXWWTDC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SureshS11,
  author       = {T. Suresh and
                  K. L. Shunmuganathan},
  title        = {Efficient Resource Sharing Architecture for Multistandard Communication
                  System},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {328640:1--328640:9},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/328640},
  doi          = {10.1155/2011/328640},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/SureshS11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ZhangQZSW11,
  author       = {Haipeng Zhang and
                  Ruisheng Qi and
                  Liang Zhang and
                  Buchun Su and
                  Dejun Wang},
  title        = {Vertical Gate {RF} {SOI} {LIGBT} for SPICs with Significantly Improved
                  Latch-Up Immunity},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {548546:1--548546:9},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/548546},
  doi          = {10.1155/2011/548546},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ZhangQZSW11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ZhouALST11,
  author       = {Nancy Ying Zhou and
                  Charles J. Alpert and
                  Zhuo Li and
                  Cliff N. Sze and
                  Louise Trevillyan},
  title        = {Shedding Physical Synthesis Area Bloat},
  journal      = {{VLSI} Design},
  volume       = {2011},
  pages        = {503025:1--503025:10},
  year         = {2011},
  url          = {https://doi.org/10.1155/2011/503025},
  doi          = {10.1155/2011/503025},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ZhouALST11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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