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@article{DBLP:journals/vlsi/AssaadS09,
  author       = {Rida S. Assaad and
                  Jos{\'{e}} Silva{-}Mart{\'{\i}}nez},
  title        = {Recent Advances on the Design of High-Gain Wideband Operational Transconductance
                  Amplifiers},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {323595:1--323595:11},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/323595},
  doi          = {10.1155/2009/323595},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/AssaadS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MohammadDLA09,
  author       = {Khader Mohammad and
                  Ayman Dodin and
                  Bao Liu and
                  Sos S. Agaian},
  title        = {Reduced Voltage Scaling in Clock Distribution Networks},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {679853:1--679853:7},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/679853},
  doi          = {10.1155/2009/679853},
  timestamp    = {Thu, 21 Dec 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/MohammadDLA09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Nilsson09,
  author       = {Peter Nilsson},
  title        = {Architectures and Arithmetic for Low Static Power Consumption in Nanoscale
                  {CMOS}},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {749272:1--749272:10},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/749272},
  doi          = {10.1155/2009/749272},
  timestamp    = {Thu, 21 Nov 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/Nilsson09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RakaiBAT09,
  author       = {Logan M. Rakai and
                  Laleh Behjat and
                  Shawki Areibi and
                  Tam{\'{a}}s Terlaky},
  title        = {A Multilevel Congestion-Based Global Router},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {537341:1--537341:13},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/537341},
  doi          = {10.1155/2009/537341},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RakaiBAT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SammanHG09,
  author       = {Faizal Arya Samman and
                  Thomas Hollstein and
                  Manfred Glesner},
  title        = {Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping
                  Management},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {941701:1--941701:15},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/941701},
  doi          = {10.1155/2009/941701},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/SammanHG09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SharifiB09,
  author       = {Mohammad Javad Sharifi and
                  Davoud Bahrepour},
  title        = {A New {XOR} Structure Based on Resonant-Tunneling High Electron Mobility
                  Transistor},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {803974:1--803974:9},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/803974},
  doi          = {10.1155/2009/803974},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/SharifiB09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/VaddiDA09,
  author       = {Ramesh Vaddi and
                  Sudeb Dasgupta and
                  R. P. Agarwal},
  title        = {Device and Circuit Design Challenges in the Digital Subthreshold Region
                  for Ultralow-Power Applications},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {283702:1--283702:14},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/283702},
  doi          = {10.1155/2009/283702},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/VaddiDA09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/XingJ09,
  author       = {Xianwu Xing and
                  Ching{-}Chuen Jong},
  title        = {Floorplan-Driven Multivoltage High-Level Synthesis},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {156751:1--156751:10},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/156751},
  doi          = {10.1155/2009/156751},
  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/XingJ09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ZhangC09,
  author       = {Min Zhang and
                  Oliver Chiu{-}sing Choy},
  title        = {Low-Cost Allocator Implementations for Networks-on-Chip Routers},
  journal      = {{VLSI} Design},
  volume       = {2009},
  pages        = {415646:1--415646:10},
  year         = {2009},
  url          = {https://doi.org/10.1155/2009/415646},
  doi          = {10.1155/2009/415646},
  timestamp    = {Sat, 24 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/ZhangC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}