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@article{DBLP:journals/integration/ChangelaZV20,
  author       = {Ankur Changela and
                  Mazad Zaveri and
                  Deepak Verma},
  title        = {{FPGA} implementation of high-performance, resource-efficient Radix-16
                  {CORDIC} rotator based {FFT} algorithm},
  journal      = {Integr.},
  volume       = {73},
  pages        = {89--100},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.03.008},
  doi          = {10.1016/J.VLSI.2020.03.008},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/ChangelaZV20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ChenC20,
  author       = {Ethan Chen and
                  Vanessa Chen},
  title        = {In-sensor time-domain classifiers using pseudo sigmoid activation
                  functions},
  journal      = {Integr.},
  volume       = {73},
  pages        = {43--49},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.03.002},
  doi          = {10.1016/J.VLSI.2020.03.002},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/ChenC20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/GutierrezL20,
  author       = {Valentin Gutierrez and
                  Gildas L{\'{e}}ger},
  title        = {An adaptive simulation framework for {AMS-RF} test quality},
  journal      = {Integr.},
  volume       = {73},
  pages        = {10--17},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.03.003},
  doi          = {10.1016/J.VLSI.2020.03.003},
  timestamp    = {Sat, 09 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/GutierrezL20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/HosseinyJ20,
  author       = {Adel Hosseiny and
                  Ghassem Jaberipur},
  title        = {Complex exponential functions: {A} high-precision hardware realization},
  journal      = {Integr.},
  volume       = {73},
  pages        = {18--29},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.02.005},
  doi          = {10.1016/J.VLSI.2020.02.005},
  timestamp    = {Mon, 28 Aug 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/HosseinyJ20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KabinDKL20,
  author       = {Ievgen Kabin and
                  Zoya Dyka and
                  Dan Klann and
                  Peter Langend{\"{o}}rfer},
  title        = {Methods increasing inherent resistance of {ECC} designs against horizontal
                  attacks},
  journal      = {Integr.},
  volume       = {73},
  pages        = {50--67},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.03.001},
  doi          = {10.1016/J.VLSI.2020.03.001},
  timestamp    = {Fri, 14 May 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/KabinDKL20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/NeunerG20,
  author       = {Maximilian Neuner and
                  Helmut Graeb},
  title        = {Verification and revision of the power-down mode for hierarchical
                  analog circuits},
  journal      = {Integr.},
  volume       = {73},
  pages        = {1--9},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.02.009},
  doi          = {10.1016/J.VLSI.2020.02.009},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/NeunerG20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RazaviR20,
  author       = {Sayyed Mohammad Razavi and
                  Seyyed Mohammad Razavi},
  title        = {An efficient and reliable MRF-based methodology for designing low-power
                  {VLSI} circuits},
  journal      = {Integr.},
  volume       = {73},
  pages        = {77--88},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.03.005},
  doi          = {10.1016/J.VLSI.2020.03.005},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/RazaviR20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/VidhyadharanDVY20,
  author       = {Sanjay Vidhyadharan and
                  Surya Shankar Dan and
                  Abhay S. Vidhyadharan and
                  Ramakant Yadav and
                  Simhadri Hariprasad},
  title        = {Novel gate-overlap tunnel {FET} based innovative ultra-low-power ternary
                  flash {ADC}},
  journal      = {Integr.},
  volume       = {73},
  pages        = {101--113},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.03.006},
  doi          = {10.1016/J.VLSI.2020.03.006},
  timestamp    = {Thu, 23 Sep 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/VidhyadharanDVY20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/VohraSG20,
  author       = {Harpreet Vohra and
                  Ashima Singh and
                  Sukhpal Singh Gill},
  title        = {An innovative two-stage data compression scheme using adaptive block
                  merging technique},
  journal      = {Integr.},
  volume       = {73},
  pages        = {68--76},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.03.004},
  doi          = {10.1016/J.VLSI.2020.03.004},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/VohraSG20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ZhangDY20,
  author       = {Zhiming Zhang and
                  Jaya Dofe and
                  Qiaoyan Yu},
  title        = {Improving power analysis attack resistance using intrinsic noise in
                  3D ICs},
  journal      = {Integr.},
  volume       = {73},
  pages        = {30--42},
  year         = {2020},
  url          = {https://doi.org/10.1016/j.vlsi.2020.02.007},
  doi          = {10.1016/J.VLSI.2020.02.007},
  timestamp    = {Wed, 27 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/ZhangDY20.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}