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@article{DBLP:journals/integration/AminS89,
  author       = {Alaaeldin A. M. Amin and
                  Kent F. Smith},
  title        = {Test generation and fault detection for {VLSI} {PPL} circuits},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {303--324},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90007-2},
  doi          = {10.1016/0167-9260(89)90007-2},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/AminS89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/BhawmikNC89,
  author       = {Sudipta Bhawmik and
                  V. K. Narang and
                  Parimal Pal Chaudhuri},
  title        = {Selecting test methodologies for PLAs and random logic modules in
                  {VLSI} circuits - an expert systems approach},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {267--281},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90005-9},
  doi          = {10.1016/0167-9260(89)90005-9},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/BhawmikNC89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/CuratelliA89,
  author       = {Francesco Curatelli and
                  P. Antognetti},
  title        = {A reconfigurable wiring algorithm for three-layer maze routing},
  journal      = {Integr.},
  volume       = {7},
  number       = {2},
  pages        = {127--149},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90034-5},
  doi          = {10.1016/0167-9260(89)90034-5},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/CuratelliA89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/EnbodyD89,
  author       = {Richard J. Enbody and
                  David H. C. Du},
  title        = {{SPYDER:} a serial/parallel goal-directed router},
  journal      = {Integr.},
  volume       = {7},
  number       = {2},
  pages        = {151--187},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90035-7},
  doi          = {10.1016/0167-9260(89)90035-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/EnbodyD89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Grabinski89,
  author       = {Hartmut Grabinski},
  title        = {An algorithm for computing the signal propagation on lossy {VLSI}
                  interconnect systems in the time domain},
  journal      = {Integr.},
  volume       = {7},
  number       = {1},
  pages        = {35--48},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90058-8},
  doi          = {10.1016/0167-9260(89)90058-8},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Grabinski89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Hwang89,
  author       = {Sun Young Hwang},
  title        = {Incremental algorithms for digital simulation},
  journal      = {Integr.},
  volume       = {7},
  number       = {1},
  pages        = {21--34},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90057-6},
  doi          = {10.1016/0167-9260(89)90057-6},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Hwang89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/JouL89,
  author       = {Jer{-}Min Jou and
                  Jau{-}Yien Lee},
  title        = {A new 3-layer rectilinear area router with obstacle avoidance},
  journal      = {Integr.},
  volume       = {7},
  number       = {1},
  pages        = {1--20},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90056-4},
  doi          = {10.1016/0167-9260(89)90056-4},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/JouL89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Joyce89,
  author       = {Jeffrey J. Joyce},
  title        = {Formal specification and verification of microprocessor systems},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {247--266},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90004-7},
  doi          = {10.1016/0167-9260(89)90004-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Joyce89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KollaM89,
  author       = {Reiner Kolla and
                  Paul Molitor},
  title        = {A note on hierarchical layer-assignment},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {213--230},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90002-3},
  doi          = {10.1016/0167-9260(89)90002-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KollaM89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KuoCS89,
  author       = {Yue{-}Sun Kuo and
                  T. C. Chern and
                  Wei{-}Kuan Shih},
  title        = {Fast algorithm for optimal layer assignment},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {231--245},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90003-5},
  doi          = {10.1016/0167-9260(89)90003-5},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KuoCS89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/LimSJ89,
  author       = {P. K. Lim and
                  Maher A. Sid{-}Ahmed and
                  Graham A. Jullien},
  title        = {{VLSI} implementation of a digital image threshold selection architecture},
  journal      = {Integr.},
  volume       = {7},
  number       = {1},
  pages        = {77--91},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90060-6},
  doi          = {10.1016/0167-9260(89)90060-6},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/LimSJ89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/MuellerWL89,
  author       = {Thomas R. Mueller and
                  D. F. Wong and
                  C. L. Liu},
  title        = {An enhanced bottom-up algorithm for floorplan design},
  journal      = {Integr.},
  volume       = {7},
  number       = {2},
  pages        = {189--201},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90036-9},
  doi          = {10.1016/0167-9260(89)90036-9},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/integration/MuellerWL89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/NiLE89,
  author       = {Lionel M. Ni and
                  Youran Lan and
                  Abdol{-}Hossein Esfahanian},
  title        = {A {VLSI} router design for hypercube multiprocessors},
  journal      = {Integr.},
  volume       = {7},
  number       = {2},
  pages        = {103--125},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90033-3},
  doi          = {10.1016/0167-9260(89)90033-3},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/NiLE89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/RaviKumarS89,
  author       = {C. P. Ravikumar and
                  Sarma Sastry},
  title        = {A hardware accelerator for hierarchical {VLSI} routing},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {283--302},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90006-0},
  doi          = {10.1016/0167-9260(89)90006-0},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/RaviKumarS89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SethA89,
  author       = {Sharad C. Seth and
                  Vishwani D. Agrawal},
  title        = {A new model for computation of probabilistic testability in combinational
                  circuits},
  journal      = {Integr.},
  volume       = {7},
  number       = {1},
  pages        = {49--75},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90059-X},
  doi          = {10.1016/0167-9260(89)90059-X},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/SethA89.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/SethA89a,
  author       = {Sharad C. Seth and
                  Vishwani D. Agrawal},
  title        = {A new model for computation of probabilistic testability in combinational
                  circuits},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {325},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90008-4},
  doi          = {10.1016/0167-9260(89)90008-4},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/SethA89a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Spaanenburg89b,
  author       = {Lambert Spaanenburg},
  title        = {Editorial},
  journal      = {Integr.},
  volume       = {7},
  number       = {1},
  pages        = {vii},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90055-2},
  doi          = {10.1016/0167-9260(89)90055-2},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Spaanenburg89b.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Spaanenburg89c,
  author       = {Lambert Spaanenburg},
  title        = {Editorial},
  journal      = {Integr.},
  volume       = {7},
  number       = {2},
  pages        = {101},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90032-1},
  doi          = {10.1016/0167-9260(89)90032-1},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Spaanenburg89c.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Spaanenburg89d,
  author       = {Lambert Spaanenburg},
  title        = {Editorial},
  journal      = {Integr.},
  volume       = {7},
  number       = {3},
  pages        = {211},
  year         = {1989},
  url          = {https://doi.org/10.1016/0167-9260(89)90001-1},
  doi          = {10.1016/0167-9260(89)90001-1},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Spaanenburg89d.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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