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@article{DBLP:journals/integration/CongHKM96,
  author       = {Jason Cong and
                  Lei He and
                  Cheng{-}Kok Koh and
                  Patrick H. Madden},
  title        = {Performance optimization of {VLSI} interconnect layout},
  journal      = {Integr.},
  volume       = {21},
  number       = {1-2},
  pages        = {1--94},
  year         = {1996},
  url          = {https://doi.org/10.1016/S0167-9260(96)00008-9},
  doi          = {10.1016/S0167-9260(96)00008-9},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/CongHKM96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/ElesKP96,
  author       = {Petru Eles and
                  Krzysztof Kuchcinski and
                  Zebo Peng},
  title        = {Synthesis of systems specified as interacting {VHDL} processes},
  journal      = {Integr.},
  volume       = {21},
  number       = {1-2},
  pages        = {113--138},
  year         = {1996},
  url          = {https://doi.org/10.1016/S0167-9260(96)00012-0},
  doi          = {10.1016/S0167-9260(96)00012-0},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/ElesKP96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/Gizdarski96,
  author       = {Emil Gizdarski},
  title        = {Built-in self-test for folded bit-line Mbit DRAMs},
  journal      = {Integr.},
  volume       = {21},
  number       = {1-2},
  pages        = {95--112},
  year         = {1996},
  url          = {https://doi.org/10.1016/S0167-9260(96)00007-7},
  doi          = {10.1016/S0167-9260(96)00007-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/Gizdarski96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/GizopoulosNP96,
  author       = {Dimitris Gizopoulos and
                  Dimitris Nikolos and
                  Antonis M. Paschalis},
  title        = {Testing {CMOS} combinational iterative logic arrays for realistic
                  faults},
  journal      = {Integr.},
  volume       = {21},
  number       = {3},
  pages        = {209--228},
  year         = {1996},
  url          = {https://doi.org/10.1016/S0167-9260(96)00000-4},
  doi          = {10.1016/S0167-9260(96)00000-4},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/GizopoulosNP96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/IsmaeelDM96,
  author       = {Asad A. Ismaeel and
                  Muhammad K. Dhodhi and
                  Rajan Mathew},
  title        = {Assignment and allocation of highly testable data paths under scan
                  optimization},
  journal      = {Integr.},
  volume       = {21},
  number       = {3},
  pages        = {191--207},
  year         = {1996},
  url          = {https://doi.org/10.1016/S0167-9260(96)00013-2},
  doi          = {10.1016/S0167-9260(96)00013-2},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/IsmaeelDM96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/KoideTWY96,
  author       = {Tetsushi Koide and
                  Masahiro Tsuchiya and
                  Shin'ichi Wakabayashi and
                  Noriyoshi Yoshida},
  title        = {A three-layer over-the-cell multi-channel router for a new cell model},
  journal      = {Integr.},
  volume       = {21},
  number       = {3},
  pages        = {171--189},
  year         = {1996},
  url          = {https://doi.org/10.1016/S0167-9260(96)00011-9},
  doi          = {10.1016/S0167-9260(96)00011-9},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/KoideTWY96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/integration/YakovlevKSK96,
  author       = {Alexandre Yakovlev and
                  Albert Koelmans and
                  Alexei L. Semenov and
                  D. J. Kinniment},
  title        = {Modelling, analysis and synthesis of asynchronous control circuits
                  using Petri nets},
  journal      = {Integr.},
  volume       = {21},
  number       = {3},
  pages        = {143--170},
  year         = {1996},
  url          = {https://doi.org/10.1016/S0167-9260(96)00010-7},
  doi          = {10.1016/S0167-9260(96)00010-7},
  timestamp    = {Thu, 20 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/integration/YakovlevKSK96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}