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@inproceedings{DBLP:conf/slip/AhmedMC16,
  author       = {Mohammad A. Ahmed and
                  Sucheta Mohapatra and
                  Malgorzata Chrzanowska{-}Jeske},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {Buffered Interconnects in 3D {IC} Layout Design},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {4:1--4:8},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947366},
  doi          = {10.1145/2947357.2947366},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/AhmedMC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/BazylevychPB16,
  author       = {Roman P. Bazylevych and
                  Marek Palasinski and
                  Lubov Bazylevych},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {Topologically-Geometric Routing},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {5:1--5:6},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947367},
  doi          = {10.1145/2947357.2947367},
  timestamp    = {Tue, 31 May 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/BazylevychPB16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ChanKL16,
  author       = {Wei{-}Ting Jonas Chan and
                  Andrew B. Kahng and
                  Jiajia Li},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {Revisiting 3DIC Benefit with Multiple Tiers},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {6:1--6:8},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947363},
  doi          = {10.1145/2947357.2947363},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/ChanKL16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/EkenBZYWLC16,
  author       = {Enes Eken and
                  Ismail Bayram and
                  Yaojun Zhang and
                  Bonan Yan and
                  Wenqing Wu and
                  Hai (Helen) Li and
                  Yiran Chen},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {Spin-Hall Assisted {STT-RAM} Design and Discussion},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {7:1--7:4},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947360},
  doi          = {10.1145/2947357.2947360},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/EkenBZYWLC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/HsuLH16,
  author       = {Chih{-}Cheng Hsu and
                  Mark Po{-}Hung Lin and
                  Masanori Hashimoto},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {Latch Clustering for Minimizing Detection-to-Boosting Latency Toward
                  Low-Power Resilient Circuits},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {2:1--2:6},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947364},
  doi          = {10.1145/2947357.2947364},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/HsuLH16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/MansoorSG16,
  author       = {Naseef Mansoor and
                  Md Shahriar Shamim and
                  Amlan Ganguly},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {A Demand-Aware Predictive Dynamic Bandwidth Allocation Mechanism for
                  Wireless Network-on-Chip},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {8:1--8:8},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947361},
  doi          = {10.1145/2947357.2947361},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/MansoorSG16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/SegalDMB16,
  author       = {Carrie Segal and
                  Aditya Dalakoti and
                  Merritt Miller and
                  Forrest Brewer},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {Connectivity Effects on Energy and Area for Neuromorphic System with
                  High Speed Asynchronous Pulse Mode Links},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {3:1--3:7},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947365},
  doi          = {10.1145/2947357.2947365},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/SegalDMB16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ThakkarCP16,
  author       = {Ishan G. Thakkar and
                  Sai Vineel Reddy Chittamuru and
                  Sudeep Pasricha},
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {A Comparative Analysis of Front-End and Back-End Compatible Silicon
                  Photonic On-Chip Interconnects},
  booktitle    = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  pages        = {1:1--1:8},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357.2947362},
  doi          = {10.1145/2947357.2947362},
  timestamp    = {Wed, 11 Aug 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/ThakkarCP16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/slip/2016,
  editor       = {Baris Taskin and
                  Tsung{-}Yi Ho},
  title        = {Proceedings of the 18th System Level Interconnect Prediction Workshop,
                  {SLIP} 2016, Austin, TX, USA, June 4, 2016},
  publisher    = {{ACM}},
  year         = {2016},
  url          = {https://doi.org/10.1145/2947357},
  doi          = {10.1145/2947357},
  isbn         = {978-1-4503-4430-2},
  timestamp    = {Wed, 16 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/2016.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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