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@inproceedings{DBLP:conf/rsp/BollengierLT21,
  author       = {Th{\'{e}}otime Bollengier and
                  Lo{\"{\i}}c Lagadec and
                  Ciprian Teodorov},
  title        = {Prototyping {FPGA} through overlays},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {15--21},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806222},
  doi          = {10.1109/RSP53691.2021.9806222},
  timestamp    = {Mon, 04 Jul 2022 08:26:36 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/BollengierLT21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/BuscherGWH21,
  author       = {Nils B{\"{u}}scher and
                  Daniel Gis and
                  Johann{-}Peter Wolff and
                  Christian Haubelt},
  title        = {Data Augmentation Framework for Smart Sensor System Development Using
                  the Sensor-in-the-Loop Prototyping Platform},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {22--28},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806209},
  doi          = {10.1109/RSP53691.2021.9806209},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/BuscherGWH21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/FerresMR21,
  author       = {Bruno Ferres and
                  Olivier Muller and
                  Fr{\'{e}}d{\'{e}}ric Rousseau},
  title        = {Integrating Quick Resource Estimators in Hardware Construction Framework
                  for Design Space Exploration},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {64--70},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806276},
  doi          = {10.1109/RSP53691.2021.9806276},
  timestamp    = {Sat, 02 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/FerresMR21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/FranceBMNB21,
  author       = {Lo{\"{\i}}c France and
                  Florent Bruguier and
                  Maria Mushtaq and
                  David Novo and
                  Pascal Benoit},
  title        = {Implementing Rowhammer Memory Corruption in the gem5 Simulator},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {36--42},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806242},
  doi          = {10.1109/RSP53691.2021.9806242},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/FranceBMNB21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/KaurKDK21,
  author       = {Harpreet Kaur and
                  Georgiy Krylov and
                  Seyed Alireza Damghani and
                  Kenneth B. Kent},
  title        = {Heterogeneous Logic Implementation for Adders in {VTR}},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {57--63},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806205},
  doi          = {10.1109/RSP53691.2021.9806205},
  timestamp    = {Sun, 04 Aug 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/KaurKDK21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/KimCPY21,
  author       = {Soobeom Kim and
                  Seunghwan Cho and
                  Eunhyeok Park and
                  Sungjoo Yoo},
  title        = {{FPGA} Prototyping of Systolic Array-based Accelerator for Low-Precision
                  Inference of Deep Neural Networks},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {1--7},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806200},
  doi          = {10.1109/RSP53691.2021.9806200},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/KimCPY21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/MagalhaesNHLN21,
  author       = {Felipe G{\"{o}}hring de Magalh{\~{a}}es and
                  Mahdi Nikdast and
                  Fabiano Hessel and
                  Odile Liboiron{-}Ladouceur and
                  Gabriela Nicolescu},
  title        = {HyCo: {A} Low-Latency Hybrid Control Plane for Optical Interconnection
                  Networks},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {50--56},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806198},
  doi          = {10.1109/RSP53691.2021.9806198},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/MagalhaesNHLN21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/MambuCDK21,
  author       = {Kevin Mambu and
                  Henri{-}Pierre Charles and
                  Julie Dumas and
                  Maha Kooli},
  title        = {Instruction Set Design Methodology for In-Memory Computing through
                  QEMU-based System Emulator},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {43--49},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806255},
  doi          = {10.1109/RSP53691.2021.9806255},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/MambuCDK21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/NeubauerMMBKR21,
  author       = {Kevin Neubauer and
                  Leonard Masing and
                  Michael Mahl and
                  J{\"{u}}rgen Becker and
                  Max E. Kramer and
                  Clemens Reichmann},
  title        = {Template-Driven and Hardware-Centric Cross-Domain {E/E} Architecture
                  Simulation},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {29--35},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806231},
  doi          = {10.1109/RSP53691.2021.9806231},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/NeubauerMMBKR21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/rsp/SorianoNB21,
  author       = {Theo Soriano and
                  David Novo and
                  Pascal Benoit},
  title        = {An FPGA-based Emulation Platform for Edge Computing Node Design Exploration},
  booktitle    = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  pages        = {8--14},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021.9806230},
  doi          = {10.1109/RSP53691.2021.9806230},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/SorianoNB21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/rsp/2021,
  title        = {{IEEE} International Workshop on Rapid System Prototyping, {RSP} 2021,
                  Paris, France, October 14, 2021},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/RSP53691.2021},
  doi          = {10.1109/RSP53691.2021},
  isbn         = {978-1-6654-6956-2},
  timestamp    = {Mon, 04 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rsp/2021.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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