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@inproceedings{DBLP:conf/asap/AbdelhamidVK24,
  author       = {Riadh Ben Abdelhamid and
                  Vladislav V{\'{a}}lek and
                  Dirk Koch},
  title        = {{SPARKLE:} {A} 1,024-Core/16,384-Thread Single {FPGA} Many-Core {RISC-V}
                  Barrel Processor Overlay},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {118--119},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00032},
  doi          = {10.1109/ASAP61560.2024.00032},
  timestamp    = {Tue, 10 Sep 2024 15:34:15 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/AbdelhamidVK24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/BottcherK24,
  author       = {Andreas B{\"{o}}ttcher and
                  Martin Kumm},
  title        = {Multiplier Design Addressing Area-Delay Trade-offs by using {DSP}
                  and Logic resources on FPGAs},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {217--225},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00051},
  doi          = {10.1109/ASAP61560.2024.00051},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/BottcherK24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/BouazizF24,
  author       = {Mohamed Bouaziz and
                  Suhaib A. Fahmy},
  title        = {Leveraging {MLIR} for Efficient Irregular-Shaped {CGRA} Overlay Design:
                  (PhD Forum Paper)},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {204--205},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00048},
  doi          = {10.1109/ASAP61560.2024.00048},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/BouazizF24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/BraatzSRRB24,
  author       = {Yannick Braatz and
                  Taha Soliman and
                  Shubham Rai and
                  Dennis Sebastian Rieber and
                  Oliver Bringmann},
  title        = {CoNAX: Towards Comprehensive Co-Design Neural Architecture Search
                  Using {HW} Abstractions},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {8--16},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00013},
  doi          = {10.1109/ASAP61560.2024.00013},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/BraatzSRRB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/CaiDNLHN24,
  author       = {Tao Cai and
                  Jianfei Dai and
                  Dejiao Niu and
                  Lei Li and
                  Zeyu Huang and
                  Qiangqiang Ni},
  title        = {A LLC-Friendly LSM-tree},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {243--244},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00057},
  doi          = {10.1109/ASAP61560.2024.00057},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/CaiDNLHN24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/CaoWSL24,
  author       = {Yasong Cao and
                  Mei Wen and
                  Junzhong Shen and
                  Zhongxing Li},
  title        = {BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms
                  {GEMM}},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {36--44},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00020},
  doi          = {10.1109/ASAP61560.2024.00020},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/CaoWSL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/CuiB24,
  author       = {Songqiao Cui and
                  Josep Balasch},
  title        = {Configurable Loop Shuffling via Instruction Set Extensions},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {45--53},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00021},
  doi          = {10.1109/ASAP61560.2024.00021},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/CuiB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/DelestracMBMCTN24,
  author       = {Paul Delestrac and
                  Jonathan Miquel and
                  Debjyoti Bhattacharjee and
                  Diksha Moolchandani and
                  Francky Catthoor and
                  Lionel Torres and
                  David Novo},
  title        = {Analyzing {GPU} Energy Consumption in Data Movement and Storage},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {143--151},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00038},
  doi          = {10.1109/ASAP61560.2024.00038},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/DelestracMBMCTN24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/FangWHWX24,
  author       = {Yude Fang and
                  Junhui Wang and
                  Libo Huang and
                  Yongwen Wang and
                  Weixia Xu},
  title        = {Out-of-Order and Recursive {RAS:} {A} Return Address Stack Design
                  on High Performance Processor},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {116--117},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00031},
  doi          = {10.1109/ASAP61560.2024.00031},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/FangWHWX24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/GajariaAG24,
  author       = {Dhruv Gajaria and
                  Tosiron Adegbija and
                  Kevin Antony Gomez},
  title        = {{CHIME:} Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory
                  Processing},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {228--236},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00053},
  doi          = {10.1109/ASAP61560.2024.00053},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/GajariaAG24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/GuiWYLWJ24,
  author       = {Yuchen Gui and
                  Qizhe Wu and
                  Wei Yuan and
                  Huawen Liang and
                  Xiaotian Wang and
                  Xi Jin},
  title        = {A FPGA-HBM-Based Hardware Streaming Accelerator for {GNN} Sampling},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {77--78},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00026},
  doi          = {10.1109/ASAP61560.2024.00026},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/GuiWYLWJ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/GutermannB24,
  author       = {Annina Gutermann and
                  J{\"{u}}rgen Becker},
  title        = {A Full-System Approach to Multi-Valued Logic Design: (PhD Forum Paper)},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {226--227},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00052},
  doi          = {10.1109/ASAP61560.2024.00052},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/GutermannB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/HuangDS24,
  author       = {Junzhe Huang and
                  Qiang Dou and
                  Li Shen},
  title        = {Extending the {RISC-V} Instruction Set for High Performance Data Compression
                  Hardware Acceleration},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {131--132},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00035},
  doi          = {10.1109/ASAP61560.2024.00035},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/HuangDS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/IsaacChassandeEDR24,
  author       = {Valentin Isaac{-}Chassande and
                  Adrian Evans and
                  Yves Durand and
                  Fr{\'{e}}d{\'{e}}ric Rousseau},
  title        = {SpDCache: Region-Based Reduction Cache for Outer-Product Sparse Matrix
                  Kernels},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {3--7},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00012},
  doi          = {10.1109/ASAP61560.2024.00012},
  timestamp    = {Thu, 03 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/IsaacChassandeEDR24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/KarrenbauerSKB24,
  author       = {Jens Karrenbauer and
                  Sven Sch{\"{o}}newald and
                  Simon C. Klein and
                  Holger Blume},
  title        = {Enhancing a Hearing Aid Processor with {ISA} Extensions Supporting
                  Flexible Fixed-Point Formats},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {176--183},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00044},
  doi          = {10.1109/ASAP61560.2024.00044},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/KarrenbauerSKB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/KautzGTBBV24,
  author       = {Frederik Kautz and
                  Sven Gesper and
                  Gia Bao Thieu and
                  Hans{-}Martin Bl{\"{u}}thgen and
                  Holger Blume and
                  Guillermo Pay{\'{a}} Vay{\'{a}}},
  title        = {Multi-Level Prototyping of a Vertical Vector {AI} Processing System},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {1--2},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00011},
  doi          = {10.1109/ASAP61560.2024.00011},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/KautzGTBBV24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/KhemiraWNTTYA24,
  author       = {Salim Khemira and
                  Xinyuan Wang and
                  Anh Nguyen and
                  Yutaka Tamiya and
                  Makoto Taiji and
                  Takahide Yoshikawa and
                  Jason Helge Anderson},
  title        = {Raising Compute Density of Molecular Dynamics Simulation Through Approximate
                  Memoization},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {195--203},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00047},
  doi          = {10.1109/ASAP61560.2024.00047},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/KhemiraWNTTYA24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/LeePHPP24,
  author       = {Uyong Lee and
                  Yeji Park and
                  Junsu Heo and
                  Sungkyung Park and
                  Chester Sungchung Park},
  title        = {Design Space Exploration of {FFT} Accelerators for {IEEE} 802.11ax
                  using High-Level Synthesis},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {120--121},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00033},
  doi          = {10.1109/ASAP61560.2024.00033},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/LeePHPP24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/LiYZYW24,
  author       = {Jiangnan Li and
                  Yazhou Yan and
                  Guowei Zhu and
                  Wenbo Yin and
                  Lingli Wang},
  title        = {An End-to-End Agile Design Framework to Improve Energy Efficiency
                  on CGRAs},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {17--18},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00014},
  doi          = {10.1109/ASAP61560.2024.00014},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/LiYZYW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/LinZY24,
  author       = {Yiyang Lin and
                  Yi Zou and
                  Yanfeng Yang},
  title        = {{CSIFA:} {A} Configurable SRAM-based In-Memory {FFT} Accelerator},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {161--162},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00040},
  doi          = {10.1109/ASAP61560.2024.00040},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/LinZY24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/LiuCMYW24,
  author       = {Yao Liu and
                  Shiyang Chen and
                  Long Ma and
                  Guolong Yang and
                  Kun Wan},
  title        = {Real-Time Order Book Building and Snapshot Generating for High Frequency
                  Trading on {FPGA}},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {71--76},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00025},
  doi          = {10.1109/ASAP61560.2024.00025},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/LiuCMYW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/LiuCZYJC24,
  author       = {Hanqing Liu and
                  Xiaole Cui and
                  Sunrui Zhang and
                  Mingqi Yin and
                  Yuanyuan Jiang and
                  Xiaoxin Cui},
  title        = {A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware
                  Memory and Compressed Weights},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {163--171},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00041},
  doi          = {10.1109/ASAP61560.2024.00041},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/LiuCZYJC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/LuoWSZXM24,
  author       = {Shengbai Luo and
                  Bo Wang and
                  Yihao Shi and
                  Xueyi Zhang and
                  Qingshan Xue and
                  Sheng Ma},
  title        = {Sparm: {A} Sparse Matrix Multiplication Accelerator Supporting Multiple
                  Dataflows},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {122--130},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00034},
  doi          = {10.1109/ASAP61560.2024.00034},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/LuoWSZXM24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/MaoLC24,
  author       = {Yingchang Mao and
                  Qiang Liu and
                  Ray C. C. Cheung},
  title        = {{MSCA:} {A} Multi-Grained Sparse Convolution Accelerator for {DNN}
                  Training},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {34--35},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00019},
  doi          = {10.1109/ASAP61560.2024.00019},
  timestamp    = {Mon, 30 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/MaoLC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/MiuraCM24,
  author       = {Shinya Miura and
                  Qiong Chang and
                  Jun Miyazaki},
  title        = {{\textdollar}k{\textdollar}-Way In-Place Merge by {CPU-GPU} Cooperative
                  Processing},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {152--160},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00039},
  doi          = {10.1109/ASAP61560.2024.00039},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/MiuraCM24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/PerottiRSCRB24,
  author       = {Matteo Perotti and
                  Michele Raeber and
                  Mattia Sinigaglia and
                  Matheus A. Cavalcante and
                  Davide Rossi and
                  Luca Benini},
  title        = {Spatzformer: An Efficient Reconfigurable Dual-Core {RISC-V} {V} Cluster
                  for Mixed Scalar-Vector Workloads},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {172--173},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00042},
  doi          = {10.1109/ASAP61560.2024.00042},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/PerottiRSCRB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/RanAZCY24,
  author       = {Zhuoheng Ran and
                  Muhammad A. A. Abdelgawad and
                  Zekai Zhang and
                  Ray C. C. Cheung and
                  Hong Yan},
  title        = {{RO-SVD:} {A} Reconfigurable Hardware Copyright Protection Framework
                  for {AIGC} Applications},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {135--142},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00037},
  doi          = {10.1109/ASAP61560.2024.00037},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/RanAZCY24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/RenkeRKB24,
  author       = {Oliver Renke and
                  Christoph Riggers and
                  Jens Karrenbauer and
                  Holger Blume},
  title        = {Design Space Exploration of Semantic Segmentation {CNN} SalsaNext
                  for Constrained Architectures},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {28--29},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00016},
  doi          = {10.1109/ASAP61560.2024.00016},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/RenkeRKB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/RutishauserMSB24,
  author       = {Georg Rutishauser and
                  Joan Mihali and
                  Moritz Scherer and
                  Luca Bonini},
  title        = {xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based
                  Edge Systems},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {206--213},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00049},
  doi          = {10.1109/ASAP61560.2024.00049},
  timestamp    = {Tue, 01 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/RutishauserMSB24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/ShimamuraWW24,
  author       = {Yuki Shimamura and
                  Minoru Watanabe and
                  Nobuya Watanabe},
  title        = {Voltage Range Evaluation of An Optically Reconfigurable Gate Array
                  {VLSI}},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {239--240},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00055},
  doi          = {10.1109/ASAP61560.2024.00055},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/ShimamuraWW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/SuW24,
  author       = {Haoran Su and
                  Nan Wu},
  title        = {Deoxys: Defensive Approximate Computing for Secure Graph Neural Networks},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {54--60},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00022},
  doi          = {10.1109/ASAP61560.2024.00022},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/SuW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/SunD24,
  author       = {Haifeng Sun and
                  Yunfeng Deng},
  title        = {A DRL-Based Multi-Priority Task Division Scheduling Strategy in IIoT},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {79--87},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00027},
  doi          = {10.1109/ASAP61560.2024.00027},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/SunD24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/SunJLLCLSDYLW24,
  author       = {Shaoyang Sun and
                  Boyin Jin and
                  Jiahang Lou and
                  Jiangnan Li and
                  Yuhang Cao and
                  Jingyuan Li and
                  Chen Shen and
                  Yuan Dai and
                  Wenbo Yin and
                  Wai{-}Shing Luk and
                  Lingli Wang},
  title        = {{MDCRA:} {A} Reconfigurable Accelerator Framework for Multiple Dataflow
                  Lanes},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {133--134},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00036},
  doi          = {10.1109/ASAP61560.2024.00036},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/SunJLLCLSDYLW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/TangS24,
  author       = {Xiqin Tang and
                  Delong Shang},
  title        = {Design of High-Performance while Energy-Efficient Microprocessor with
                  Novel Asynchronous Techniques: (PhD Forum Paper)},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {247--248},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00059},
  doi          = {10.1109/ASAP61560.2024.00059},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/TangS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/WalterAHT24,
  author       = {Dominik Walter and
                  Thomas Adamtschuk and
                  Frank Hannig and
                  J{\"{u}}rgen Teich},
  title        = {Analysis and Optimization of Block {LU} Decomposition for Execution
                  on Tightly Coupled Processor Arrays},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {97--106},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00029},
  doi          = {10.1109/ASAP61560.2024.00029},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/WalterAHT24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/WangZWH24,
  author       = {Hongbin Wang and
                  Yi Zou and
                  Guohua Wen and
                  Junfeng Hu},
  title        = {Memory Access Acceleration Through Architecture Design for Edge SoCs},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {30--31},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00017},
  doi          = {10.1109/ASAP61560.2024.00017},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/WangZWH24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/WonKLLBPSC24,
  author       = {Dong{-}eon Won and
                  Yeeun Kim and
                  Janghwan Lee and
                  Minjae Lee and
                  Jonghyun Bae and
                  Jongjoo Park and
                  Jeongyong Song and
                  Jungwook Choi},
  title        = {{ISP2DLA:} Automated Deep Learning Accelerator Design for On-Sensor
                  Image Signal Processing},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {237--238},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00054},
  doi          = {10.1109/ASAP61560.2024.00054},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/WonKLLBPSC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/WygrzywalskiS24,
  author       = {Mateusz Wygrzywalski and
                  Robert Szczygiel},
  title        = {Lightweight Extension of {RISC-V} Core for NTT-like Algorithms: (PhD
                  Forum Paper)},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {241--242},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00056},
  doi          = {10.1109/ASAP61560.2024.00056},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/WygrzywalskiS24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/XuYCYW24,
  author       = {Zhenyu Xu and
                  Miaoxiang Yu and
                  Jillian Cai and
                  Qing Yang and
                  Tao Wei},
  title        = {TwinStep Network (TwNet): a Neuron-Centric Architecture Achieving
                  Rapid Training},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {88--96},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00028},
  doi          = {10.1109/ASAP61560.2024.00028},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/XuYCYW24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/YangKP24,
  author       = {Yang Yang and
                  Rajgopal Kannan and
                  Viktor K. Prasanna},
  title        = {A Framework for Generating Accelerators for Homomorphic Encryption
                  Operations on FPGAs},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {61--70},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00023},
  doi          = {10.1109/ASAP61560.2024.00023},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/YangKP24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/YuRWA24,
  author       = {Tianyi Yu and
                  Omar Ragheb and
                  Stephen Wicklund and
                  Jason Helge Anderson},
  title        = {MLIR-to-CGRA: {A} Versatile MLIR-Based Compiler Framework for CGRAs},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {184--192},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00045},
  doi          = {10.1109/ASAP61560.2024.00045},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/YuRWA24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/YueLXF24,
  author       = {Shipeng Yue and
                  Honghao Liang and
                  Xinpeng Xing and
                  Haigang Feng},
  title        = {{SLICE} Matrix: {A} Memory Access Scheduling Policy for Multicore
                  Network Processors},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {174--175},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00043},
  doi          = {10.1109/ASAP61560.2024.00043},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/YueLXF24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/ZhaiZX24,
  author       = {Qingchen Zhai and
                  Zhiwei Zhang and
                  Ruozhou Xiao},
  title        = {{LLM} Based End-to-end Branch Predictor Optimization Generator},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {214--216},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00050},
  doi          = {10.1109/ASAP61560.2024.00050},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/ZhaiZX24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/ZhangC24,
  author       = {Zekai Zhang and
                  Ray Chak Chung Cheung},
  title        = {Design of Light-Weight Encryption Algorithm Based on {RISC-V} Platform:
                  (PhD Forum Paper)},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {193--194},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00046},
  doi          = {10.1109/ASAP61560.2024.00046},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/ZhangC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/ZhangGFWL24,
  author       = {Zehuan Zhang and
                  Matej Genci and
                  Hongxiang Fan and
                  Andreas Wetscherek and
                  Wayne Luk},
  title        = {Accelerating {MRI} Uncertainty Estimation with Mask-Based Bayesian
                  Neural Network},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {107--115},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00030},
  doi          = {10.1109/ASAP61560.2024.00030},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/ZhangGFWL24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/ZhangZCH24,
  author       = {Yuanhai Zhang and
                  Shuai Zhao and
                  Gang Chen and
                  Kai Huang},
  title        = {Fault-tolerant {DAG} Scheduling with Runtime Reconfiguration on Multicore
                  Real-Time Systems},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {19--27},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00015},
  doi          = {10.1109/ASAP61560.2024.00015},
  timestamp    = {Sun, 06 Oct 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/ZhangZCH24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/ZhaoHZ24,
  author       = {Kangli Zhao and
                  Anping He and
                  Di Zhao},
  title        = {Research on High-Efficiency Asynchronous Superscalar Processors: (PhD
                  Forum Paper)},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {245--246},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00058},
  doi          = {10.1109/ASAP61560.2024.00058},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/ZhaoHZ24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/ZhaoY24,
  author       = {Tenghao Zhao and
                  Zhaohui Ye},
  title        = {ZeroVex: {A} Scalable and High-performance {RISC-V} Vector Processor
                  Core for Embedded Systems},
  booktitle    = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  pages        = {32--33},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024.00018},
  doi          = {10.1109/ASAP61560.2024.00018},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/ZhaoY24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/asap/2024,
  title        = {35th {IEEE} International Conference on Application-specific Systems,
                  Architectures and Processors, {ASAP} 2024, Hong Kong, July 24-26,
                  2024},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ASAP61560.2024},
  doi          = {10.1109/ASAP61560.2024},
  isbn         = {979-8-3503-4963-4},
  timestamp    = {Tue, 10 Sep 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/asap/2024.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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