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@article{DBLP:journals/trets/AlbartusEMFPT24,
author = {Nils Albartus and
Maik Ender and
Jan{-}Niklas M{\"{o}}ller and
Marc Fyrbiak and
Christof Paar and
Russell Tessier},
title = {On the Malicious Potential of Xilinx's Internal Configuration Access
Port {(ICAP)}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {26:1--26:28},
year = {2024},
url = {https://doi.org/10.1145/3633204},
doi = {10.1145/3633204},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AlbartusEMFPT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AnupreethamIHBKMNBCS24,
author = {Anupreetham Anupreetham and
Mohamed Ibrahim and
Mathew Hall and
Andrew Boutros and
Ajay Kuzhively and
Abinash Mohanty and
Eriko Nurvitadhi and
Vaughn Betz and
Yu Cao and
Jae{-}Sun Seo},
title = {High Throughput FPGA-Based Object Detection via Algorithm-Hardware
Co-Design},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {1:1--1:20},
year = {2024},
url = {https://doi.org/10.1145/3634919},
doi = {10.1145/3634919},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AnupreethamIHBKMNBCS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BaoHXJ24,
author = {Tianyou Bao and
Pengzhou He and
Jiafeng Xie and
H. S. Jacinto},
title = {{AEKA:} {FPGA} Implementation of Area-Efficient Karatsuba Accelerator
for Ring-Binary-LWE-Based Lightweight {PQC}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {29:1--29:23},
year = {2024},
url = {https://doi.org/10.1145/3637215},
doi = {10.1145/3637215},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BaoHXJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BruinVWJC24,
author = {Barry de Bruin and
Kanishkan Vadivel and
Mark Wijtvliet and
Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen and
Henk Corporaal},
title = {R-Blocks: an Energy-Efficient, Flexible, and Programmable {CGRA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {34:1--34:34},
year = {2024},
url = {https://doi.org/10.1145/3656642},
doi = {10.1145/3656642},
timestamp = {Thu, 04 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BruinVWJC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CamposMTDGMD24,
author = {Javier Campos and
Jovan Mitrevski and
Nhan Tran and
Zhen Dong and
Amir Gholaminejad and
Michael W. Mahoney and
Javier M. Duarte},
title = {End-to-end codesign of Hessian-aware quantized neural networks for
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {36:1--36:22},
year = {2024},
url = {https://doi.org/10.1145/3662000},
doi = {10.1145/3662000},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/CamposMTDGMD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CarrilKRFHKGM24,
author = {Xavier Carril and
Charalampos Kardaris and
Jordi Ribes{-}Gonz{\'{a}}lez and
Oriol Farr{\`{a}}s and
Carles Hern{\'{a}}ndez and
Vatistas Kostalabros and
Joel Ulises Gonz{\'{a}}lez{-}Jim{\'{e}}nez and
Miquel Moret{\'{o}}},
title = {Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber
and CRYSTALS-Dilithium},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {41:1--41:26},
year = {2024},
url = {https://doi.org/10.1145/3675172},
doi = {10.1145/3675172},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/CarrilKRFHKGM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenCZLZLYDYW24,
author = {Sichao Chen and
Chang Cai and
Su Zheng and
Jiangnan Li and
Guowei Zhu and
Jingyuan Li and
Yazhou Yan and
Yuan Dai and
Wenbo Yin and
Lingli Wang},
title = {HierCGRA: {A} Novel Framework for Large-scale {CGRA} with Hierarchical
Modeling and Automated Design Space Exploration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {35:1--35:31},
year = {2024},
url = {https://doi.org/10.1145/3656176},
doi = {10.1145/3656176},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChenCZLZLYDYW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenJHHM24,
author = {Jeffrey Chen and
Sang{-}Woo Jun and
Sehwan Hong and
Warrick He and
Jinyeong Moon},
title = {Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time
Inference at the Edge},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {16:1--16:25},
year = {2024},
url = {https://doi.org/10.1145/3629979},
doi = {10.1145/3629979},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChenJHHM24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenNKFSDTKB24,
author = {Kuan{-}Yu Chen and
Thomas Mason Nelson and
Alireza Khadem and
Morteza Fayazi and
Sanjay Sri Vallabh Singapuram and
Ronald G. Dreslinski and
Nishil Talati and
Hun{-}Seok Kim and
David T. Blaauw},
title = {Canalis: {A} Throughput-Optimized Framework for Real-Time Stream Processing
of Wireless Communication},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {61:1--61:32},
year = {2024},
url = {https://doi.org/10.1145/3695880},
doi = {10.1145/3695880},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ChenNKFSDTKB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DannRF24,
author = {Jonas Dann and
Daniel Ritter and
Holger Fr{\"{o}}ning},
title = {GraphScale: Scalable Processing on FPGAs for {HBM} and Large Graphs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {22:1--22:23},
year = {2024},
url = {https://doi.org/10.1145/3616497},
doi = {10.1145/3616497},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DannRF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DrewesSWRHMKR24,
author = {Colin Drewes and
Tyler Sheaves and
Olivia Weng and
Keegan Ryan and
Bill Hunter and
Christopher McCarty and
Ryan Kastner and
Dustin Richmond},
title = {Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery
in Cross-Platform Time-to-Digital Converters},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {49:1--49:30},
year = {2024},
url = {https://doi.org/10.1145/3666092},
doi = {10.1145/3666092},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DrewesSWRHMKR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DuLZGLSZXZ24,
author = {Linfeng Du and
Tingyuan Liang and
Xiaofeng Zhou and
Jinming Ge and
Shangkun Li and
Sharad Sinha and
Jieru Zhao and
Zhiyao Xie and
Wei Zhang},
title = {{FADO:} Floorplan-Aware Directive Optimization Based on Synthesis
and Analytical Models for High-Level Synthesis Designs on Multi-Die
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {47:1--47:33},
year = {2024},
url = {https://doi.org/10.1145/3653458},
doi = {10.1145/3653458},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DuLZGLSZXZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FahmyB24,
author = {Suhaib A. Fahmy and
Jason D. Bakos},
title = {Introduction to the Special Section on {FPGA} 2023},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {43:1--43:2},
year = {2024},
url = {https://doi.org/10.1145/3695841},
doi = {10.1145/3695841},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/FahmyB24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FanHLXGHP24,
author = {Zimeng Fan and
Wei Hu and
Fang Liu and
Dian Xu and
Hong Guo and
Yanxiang He and
Min Peng},
title = {A Hardware Design Framework for Computer Vision Models Based on Reconfigurable
Devices},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {2:1--2:31},
year = {2024},
url = {https://doi.org/10.1145/3635157},
doi = {10.1145/3635157},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/FanHLXGHP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GajjarKAFCCPI24,
author = {Archit Gajjar and
Priyank Kashyap and
Aydin Aysu and
Paul Franzon and
Yongjin Choi and
Chris Cheng and
Giacomo Pedretti and
Jim Ignowski},
title = {{RD-FAXID:} Ransomware Detection with FPGA-Accelerated XGBoost},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {56:1--56:33},
year = {2024},
url = {https://doi.org/10.1145/3688396},
doi = {10.1145/3688396},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GajjarKAFCCPI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GohringerKK24,
author = {Diana G{\"{o}}hringer and
Georgios Keramidas and
Akash Kumar},
title = {Introduction to the {FPL} 2021 Special Section},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {13:1--13:2},
year = {2024},
url = {https://doi.org/10.1145/3635115},
doi = {10.1145/3635115},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GohringerKK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GribokPL24,
author = {Sergey Gribok and
Bogdan Pasca and
Martin Langhammer},
title = {{CSAIL2019} Crypto-Puzzle Solver Architecture},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {44:1--44:32},
year = {2024},
url = {https://doi.org/10.1145/3639056},
doi = {10.1145/3639056},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GribokPL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HaaseCGG24,
author = {Julian Haase and
Najdet Charaf and
Alexander Gro{\ss} and
Diana G{\"{o}}hringer},
title = {NC-Library: Expanding SystemC Capabilities for Nested reConfigurable
Hardware Modelling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {37:1--37:29},
year = {2024},
url = {https://doi.org/10.1145/3662001},
doi = {10.1145/3662001},
timestamp = {Tue, 24 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/HaaseCGG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HaslerH24,
author = {Jennifer Hasler and
Cong Hao},
title = {Programmable Analog System Benchmarks Leading to Efficient Analog
Computation Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {12:1--12:25},
year = {2024},
url = {https://doi.org/10.1145/3625298},
doi = {10.1145/3625298},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HaslerH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HirtumCGKRLP24,
author = {Lennart Van Hirtum and
Patrick De Causmaecker and
Jens Goemaere and
Tobias Kenter and
Heinrich Riebler and
Michael Lass and
Christian Plessl},
title = {A Computation of the Ninth Dedekind Number Using {FPGA} Supercomputing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {40:1--40:28},
year = {2024},
url = {https://doi.org/10.1145/3674147},
doi = {10.1145/3674147},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/HirtumCGKRLP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HonoratDMN24,
author = {Alexandre Honorat and
Micka{\"{e}}l Dardaillon and
Hugo Miomandre and
Jean{-}Fran{\c{c}}ois Nezan},
title = {Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis
Workflow},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {8:1--8:26},
year = {2024},
url = {https://doi.org/10.1145/3626103},
doi = {10.1145/3626103},
timestamp = {Sat, 04 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HonoratDMN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HossfeldDNBP24,
author = {Konstantin Ho{\ss}feld and
Hans Jakob Damsgaard and
Jari Nurmi and
Michaela Blott and
Thomas B. Preu{\ss}er},
title = {High-efficiency Compressor Trees for Latest {AMD} FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {30:1--30:32},
year = {2024},
url = {https://doi.org/10.1145/3645097},
doi = {10.1145/3645097},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HossfeldDNBP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/IfrimLP24,
author = {Rares Ifrim and
Dumitrel Loghin and
Decebal Popescu},
title = {A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations
of Elliptic Curve Cryptography for Blockchain},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {62:1--62:33},
year = {2024},
url = {https://doi.org/10.1145/3696422},
doi = {10.1145/3696422},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/IfrimLP24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JaiyeobaS24,
author = {Oluwole Jaiyeoba and
Kevin Skadron},
title = {Dynamic-ACTS - {A} Dynamic Graph Analytics Accelerator For HBM-Enabled
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {48:1--48:29},
year = {2024},
url = {https://doi.org/10.1145/3662002},
doi = {10.1145/3662002},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/JaiyeobaS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JellumSLO24,
author = {Erling Rennemo Jellum and
Martin Schoeberl and
Edward Ashford Lee and
Milica Orlandic},
title = {Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical
Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {55:1--55:30},
year = {2024},
url = {https://doi.org/10.1145/3672083},
doi = {10.1145/3672083},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/JellumSLO24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JiaZLYZZXLLYWZWLPWTXLS24,
author = {Xijie Jia and
Yu Zhang and
Guangdong Liu and
Xinlin Yang and
Tianyu Zhang and
Jia Zheng and
Dongdong Xu and
Zhuohuan Liu and
Mengke Liu and
Xiaoyang Yan and
Hong Wang and
Rongzhang Zheng and
Li Wang and
Dong Li and
Satyaprakash Pareek and
Jian Weng and
Lu Tian and
Dongliang Xie and
Hong Luo and
Yi Shan},
title = {{XVDPU:} {A} High-Performance {CNN} Accelerator on the Versal Platform
Powered by the {AI} Engine},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {20:1--20:24},
year = {2024},
url = {https://doi.org/10.1145/3617836},
doi = {10.1145/3617836},
timestamp = {Wed, 19 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JiaZLYZZXLLYWZWLPWTXLS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KalomirosVV24,
author = {John A. Kalomiros and
John V. Vourvoulakis and
Stavros Vologiannidis},
title = {A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm:
An Efficient Implementation for the Stratix {V} and Zynq UltraScale+
{FPGA} Technology},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {5:1--5:25},
year = {2024},
url = {https://doi.org/10.1145/3615869},
doi = {10.1145/3615869},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KalomirosVV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KeilbartGCMWS24,
author = {Chris Keilbart and
Yuhui Gao and
Martin Chua and
Eric Matthews and
Steven J. E. Wilton and
Lesley Shannon},
title = {Designing an IEEE-Compliant {FPU} that Supports Configurable Precision
for Soft Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {33:1--33:32},
year = {2024},
url = {https://doi.org/10.1145/3650036},
doi = {10.1145/3650036},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KeilbartGCMWS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KhanHK24,
author = {Babar Khan and
Carsten Heinz and
Andreas Koch},
title = {The Open-source DeLiBA2 Hardware/Software Framework for Distributed
Storage Accelerators},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {23:1--23:32},
year = {2024},
url = {https://doi.org/10.1145/3624482},
doi = {10.1145/3624482},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KhanHK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KhattiTBBCGCF24,
author = {Moazin Khatti and
Xingyu Tian and
Ahmad Sedigh Baroughi and
Akhil Raj Baranwal and
Yuze Chi and
Licheng Guo and
Jason Cong and
Zhenman Fang},
title = {{PASTA:} Programming and Automation Support for Scalable Task-Parallel
{HLS} Programs on Modern Multi-Die FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {42:1--42:31},
year = {2024},
url = {https://doi.org/10.1145/3676849},
doi = {10.1145/3676849},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KhattiTBBCGCF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KochS24,
author = {Andreas Koch and
Kentaro Sano},
title = {Introduction to the Special Issue on {FPL} 2022},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {19:1--19:3},
year = {2024},
url = {https://doi.org/10.1145/3643474},
doi = {10.1145/3643474},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KochS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiLSFXH24,
author = {Yonggen Li and
Xin Li and
Haibin Shen and
Jicong Fan and
Yanfeng Xu and
Kejie Huang},
title = {An All-digital Compute-in-memory {FPGA} Architecture for Deep Learning
Acceleration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {18:1--18:27},
year = {2024},
url = {https://doi.org/10.1145/3640469},
doi = {10.1145/3640469},
timestamp = {Thu, 20 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiLSFXH24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiXSZLJ24,
author = {Kexin Li and
Shaoxian Xu and
Zhiyuan Shao and
Ran Zheng and
Xiaofei Liao and
Hai Jin},
title = {ScalaBFS2: {A} High-performance {BFS} Accelerator on an HBM-enhanced
{FPGA} Chip},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {32:1--32:39},
year = {2024},
url = {https://doi.org/10.1145/3650037},
doi = {10.1145/3650037},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiXSZLJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiYCDMHC24,
author = {Guangyan Li and
Zewen Ye and
Donglong Chen and
Wangchen Dai and
Gaoyu Mao and
Kejie Huang and
Ray C. C. Cheung},
title = {ProgramGalois: {A} Programmable Generator of Radix-4 Discrete Galois
Transformation Architecture for Lattice-Based Cryptography},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {53:1--53:32},
year = {2024},
url = {https://doi.org/10.1145/3689437},
doi = {10.1145/3689437},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiYCDMHC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiZZWZLWZC24,
author = {Yuqi Li and
Kehao Zhao and
Jieru Zhao and
Qirui Wang and
Shuda Zhong and
Nageswara Lalam and
Ruishu F. Wright and
Peipei Zhou and
Kevin P. Chen},
title = {FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber
Sensor System for Pedestrian Recognition},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {57:1--57:30},
year = {2024},
url = {https://doi.org/10.1145/3690389},
doi = {10.1145/3690389},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiZZWZLWZC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuCLYLS24,
author = {Yajing Liu and
Ruiqi Chen and
Shuyang Li and
Jing Yang and
Shun Li and
Bruno da Silva},
title = {FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art
to Future Opportunities},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {59:1--59:37},
year = {2024},
url = {https://doi.org/10.1145/3687480},
doi = {10.1145/3687480},
timestamp = {Sun, 08 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuCLYLS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuLYC24,
author = {Zhengyan Liu and
Qiang Liu and
Shun Yan and
Ray C. C. Cheung},
title = {An Efficient FPGA-based Depthwise Separable Convolutional Neural Network
Accelerator with Hardware Pruning},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {15:1--15:20},
year = {2024},
url = {https://doi.org/10.1145/3615661},
doi = {10.1145/3615661},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiuLYC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuLZHLZHHZJ24,
author = {Chaoqiang Liu and
Xiaofei Liao and
Long Zheng and
Yu Huang and
Haifeng Liu and
Yi Zhang and
Haiheng He and
Haoyan Huang and
Jingyi Zhou and
Hai Jin},
title = {{L-FNNG:} Accelerating Large-Scale {KNN} Graph Construction on {CPU-FPGA}
Heterogeneous Platform},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {46:1--46:29},
year = {2024},
url = {https://doi.org/10.1145/3652609},
doi = {10.1145/3652609},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuLZHLZHHZJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LopezValdiviesoC24,
author = {Jonathan Lopez{-}Valdivieso and
Ren{\'{e}} Cumplido},
title = {Design and Implementation of Hardware-Software Architecture Based
on Hashes for {SPHINCS+}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {54:1--54:22},
year = {2024},
url = {https://doi.org/10.1145/3653459},
doi = {10.1145/3653459},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LopezValdiviesoC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuAF24,
author = {Alec Lu and
Jahanvi Narendra Agrawal and
Zhenman Fang},
title = {{SQL2FPGA:} Automated Acceleration of {SQL} Query Processing on Modern
{CPU-FPGA} Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {39:1--39:28},
year = {2024},
url = {https://doi.org/10.1145/3674843},
doi = {10.1145/3674843},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LuAF24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MaschiA24,
author = {Fabio Maschi and
Gustavo Alonso},
title = {Strega: An {HTTP} Server for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {3:1--3:27},
year = {2024},
url = {https://doi.org/10.1145/3611312},
doi = {10.1145/3611312},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MaschiA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MouraC24,
author = {Rafael F{\~{a}}o de Moura and
Luigi Carro},
title = {Reprogrammable Non-Linear Circuits Using ReRAM for {NN} Accelerators},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {7:1--7:19},
year = {2024},
url = {https://doi.org/10.1145/3617894},
doi = {10.1145/3617894},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MouraC24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NikolicI24,
author = {Stefan Nikolic and
Paolo Ienne},
title = {Exploring {FPGA} Switch-Blocks without Explicitly Listing Connectivity
Patterns},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {14:1--14:39},
year = {2024},
url = {https://doi.org/10.1145/3597417},
doi = {10.1145/3597417},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NikolicI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NoyezMPV24,
author = {Louis Noyez and
Nadia El Mrabet and
Olivier Potin and
Pascal V{\'{e}}ron},
title = {Montgomery Multiplication Scalable Systolic Designs Optimized for
{DSP48E2}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {9:1--9:31},
year = {2024},
url = {https://doi.org/10.1145/3624571},
doi = {10.1145/3624571},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NoyezMPV24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/QiuMGCLYW24,
author = {Yunhui Qiu and
Yiqing Mao and
Xuchen Gao and
Sichao Chen and
Jiangnan Li and
Wenbo Yin and
Lingli Wang},
title = {{FDRA:} {A} Framework for a Dynamically Reconfigurable Accelerator
Supporting Multi-Level Parallelism},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {4:1--4:26},
year = {2024},
url = {https://doi.org/10.1145/3614224},
doi = {10.1145/3614224},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/QiuMGCLYW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ReisVN24,
author = {Miguel Reis and
M{\'{a}}rio P. V{\'{e}}stias and
Hor{\'{a}}cio C. Neto},
title = {Designing Deep Learning Models on {FPGA} with Multiple Heterogeneous
Engines},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {6:1--6:30},
year = {2024},
url = {https://doi.org/10.1145/3615870},
doi = {10.1145/3615870},
timestamp = {Sat, 04 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ReisVN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SahooUK24,
author = {Siva Satyendra Sahoo and
Salim Ullah and
Akash Kumar},
title = {\emph{AxOMaP}: Designing FPGA-based Approximate Arithmetic Operators
using Mathematical Programming},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {31:1--31:28},
year = {2024},
url = {https://doi.org/10.1145/3648694},
doi = {10.1145/3648694},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SahooUK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SaniY24,
author = {Sajjad Rostami Sani and
Andy Gean Ye},
title = {Evaluating the Impact of Using Multiple-Metal Layers on the Layout
Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {17:1--17:29},
year = {2024},
url = {https://doi.org/10.1145/3639055},
doi = {10.1145/3639055},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SaniY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SinghMLCMN24,
author = {Satwant Singh and
Carlos Enrique Montenegro{-}Mar{\'{\i}}n and
Yun (Eric) Liang and
Yao Chen and
Nele Mentens and
Raymond Nijssen},
title = {Introduction to the Special Issue on FPGA-based Embedded Systems for
Industrial and IoT Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {52:1--52:2},
year = {2024},
url = {https://doi.org/10.1145/3698202},
doi = {10.1145/3698202},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/SinghMLCMN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SoleimaniCL24,
author = {Parastoo Soleimani and
David W. Capson and
Kin Fun Li},
title = {A Partitioned {CAM} Architecture with {FPGA} Acceleration for Binary
Descriptor Matching},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {10:1--10:21},
year = {2024},
url = {https://doi.org/10.1145/3624749},
doi = {10.1145/3624749},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SoleimaniCL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SozzoCS24,
author = {Emanuele Del Sozzo and
Davide Conficconi and
Kentaro Sano},
title = {Across Time and Space: Senju's Approach for Scaling Iterative Stencil
Loop Accelerators on Single and Multiple FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {28:1--28:33},
year = {2024},
url = {https://doi.org/10.1145/3634920},
doi = {10.1145/3634920},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SozzoCS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TangLCZMZYW24,
author = {Enhao Tang and
Shun Li and
Ruiqi Chen and
Hao Zhou and
Yuhanxiao Ma and
Haoyang Zhang and
Jun Yu and
Kun Wang},
title = {Graph-OPU: {A} Highly Flexible FPGA-Based Overlay Processor for Graph
Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {58:1--58:33},
year = {2024},
url = {https://doi.org/10.1145/3691636},
doi = {10.1145/3691636},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/TangLCZMZYW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TrautmannKBWT24,
author = {Jens Trautmann and
Paul Kr{\"{u}}ger and
Andreas Becher and
Stefan Wildermann and
J{\"{u}}rgen Teich},
title = {Design, Calibration, and Evaluation of Real-time Waveform Matching
on an FPGA-based Digitizer at 10 GS/s},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {24:1--24:28},
year = {2024},
url = {https://doi.org/10.1145/3635719},
doi = {10.1145/3635719},
timestamp = {Thu, 04 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TrautmannKBWT24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TrochatosES24,
author = {Theodoros Trochatos and
Anthony Etim and
Jakub Szefer},
title = {Covert-channels in FPGA-enabled SmartSSDs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {27:1--27:23},
year = {2024},
url = {https://doi.org/10.1145/3635312},
doi = {10.1145/3635312},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TrochatosES24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WengMLKASMKDDK24,
author = {Olivia Weng and
Gabriel Marcano and
Vladimir Loncar and
Alireza Khodamoradi and
G. Abarajithan and
Nojan Sheybani and
Andres Meza and
Farinaz Koushanfar and
Kristof Denolf and
Javier Mauricio Duarte and
Ryan Kastner},
title = {Tailor: Altering Skip Connections for Resource-Efficient Inference},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {1},
pages = {11:1--11:23},
year = {2024},
url = {https://doi.org/10.1145/3624990},
doi = {10.1145/3624990},
timestamp = {Mon, 15 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WengMLKASMKDDK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WilsonBCW24,
author = {Andrew Elbert Wilson and
Nathan Baker and
Ethan Campbell and
Michael J. Wirthlin},
title = {Improving Fault Tolerance for {FPGA} SoCs through Post-Radiation Design
Analysis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {50:1--50:21},
year = {2024},
url = {https://doi.org/10.1145/3674841},
doi = {10.1145/3674841},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WilsonBCW24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WongZL24,
author = {Linus Y. Wong and
Jialiang Zhang and
Jing Jane Li},
title = {{DONGLE} 2.0: Direct FPGA-Orchestrated NVMe Storage for {HLS}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {45:1--45:32},
year = {2024},
url = {https://doi.org/10.1145/3650038},
doi = {10.1145/3650038},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WongZL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WuZYPY24,
author = {Zi{-}Ming Wu and
Meng{-}Yuan Zhao and
Bin Yan and
Jeng{-}Shyang Pan and
Hong{-}Mei Yang},
title = {{FPGA} Accelerated Implementation of 3D Mesh Secret Sharing Based
on Symmetric Similarity of Model},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {4},
pages = {60:1--60:19},
year = {2024},
url = {https://doi.org/10.1145/3689049},
doi = {10.1145/3689049},
timestamp = {Sun, 22 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WuZYPY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/XiaoPNHD24,
author = {Yuanlong Xiao and
Dongjoon Park and
Zeyu Jason Niu and
Aditya Hota and
Andr{\'{e}} DeHon},
title = {ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental
{FPGA} Compilation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {21:1--21:28},
year = {2024},
url = {https://doi.org/10.1145/3617837},
doi = {10.1145/3617837},
timestamp = {Thu, 04 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/XiaoPNHD24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/XuJXQ24,
author = {Shiyao Xu and
Jingfei Jiang and
Jinwei Xu and
Xifu Qian},
title = {Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated
Generator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {38:1--38:30},
year = {2024},
url = {https://doi.org/10.1145/3665896},
doi = {10.1145/3665896},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/XuJXQ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YangLFLZX24,
author = {Geng Yang and
Jie Lei and
Zhenman Fang and
Yunsong Li and
Jiaqing Zhang and
Weiying Xie},
title = {HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural
Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {2},
pages = {25:1--25:24},
year = {2024},
url = {https://doi.org/10.1145/3631610},
doi = {10.1145/3631610},
timestamp = {Tue, 18 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YangLFLZX24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhuangLYYJLDNJHSCCZ24,
author = {Jinming Zhuang and
Jason Lau and
Hanchen Ye and
Zhuoping Yang and
Shixin Ji and
Jack Lo and
Kristof Denolf and
Stephen Neuendorffer and
Alex K. Jones and
Jingtong Hu and
Yiyu Shi and
Deming Chen and
Jason Cong and
Peipei Zhou},
title = {{CHARM} 2.0: Composing Heterogeneous Accelerators for Deep Learning
on Versal {ACAP} Architecture},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {17},
number = {3},
pages = {51:1--51:31},
year = {2024},
url = {https://doi.org/10.1145/3686163},
doi = {10.1145/3686163},
timestamp = {Wed, 06 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ZhuangLYYJLDNJHSCCZ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AbdelhamidYB23,
author = {Riadh Ben Abdelhamid and
Yoshiki Yamaguchi and
Taisuke Boku},
title = {A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die
{FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {15:1--15:33},
year = {2023},
url = {https://doi.org/10.1145/3547657},
doi = {10.1145/3547657},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/AbdelhamidYB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AroraBBASHGKJ23,
author = {Aman Arora and
Atharva Bhamburkar and
Aatman Borda and
Tanmay Anand and
Rishabh Sehgal and
Bagus Hanindhito and
Pierre{-}Emmanuel Gaillardon and
Jaydeep Kulkarni and
Lizy K. John},
title = {CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {50:1--50:34},
year = {2023},
url = {https://doi.org/10.1145/3603504},
doi = {10.1145/3603504},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AroraBBASHGKJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AttiaB23,
author = {Sameh Attia and
Vaughn Betz},
title = {Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based
Co-Simulation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {31:1--31:24},
year = {2023},
url = {https://doi.org/10.1145/3552521},
doi = {10.1145/3552521},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AttiaB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BasalamaSWGC23,
author = {Suhail Basalama and
Atefeh Sohrabizadeh and
Jie Wang and
Licheng Guo and
Jason Cong},
title = {FlexCNN: An End-to-end Framework for Composing {CNN} Accelerators
on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {23:1--23:32},
year = {2023},
url = {https://doi.org/10.1145/3570928},
doi = {10.1145/3570928},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BasalamaSWGC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BucknallF23,
author = {Alex R. Bucknall and
Suhaib A. Fahmy},
title = {ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration
of {FPGA} SoCs at the Edge},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {34:1--34:33},
year = {2023},
url = {https://doi.org/10.1145/3585521},
doi = {10.1145/3585521},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BucknallF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChangZZ23,
author = {Liang Chang and
Xin Zhao and
Jun Zhou},
title = {{ADAS:} {A} High Computational Utilization Dynamic Reconfigurable
Hardware Accelerator for Super Resolution},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {47:1--47:22},
year = {2023},
url = {https://doi.org/10.1145/3570927},
doi = {10.1145/3570927},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChangZZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChengJWC23,
author = {Jianyi Cheng and
Lana Josipovic and
John Wickerson and
George A. Constantinides},
title = {Parallelising Control Flow in Dynamic-scheduling High-level Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {55:1--55:32},
year = {2023},
url = {https://doi.org/10.1145/3599973},
doi = {10.1145/3599973},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ChengJWC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChoiSSDC23,
author = {Young Kyu Choi and
Carlos Santillana and
Yujia Shen and
Adnan Darwiche and
Jason Cong},
title = {{FPGA} Acceleration of Probabilistic Sentential Decision Diagrams
with High-level Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {18:1--18:22},
year = {2023},
url = {https://doi.org/10.1145/3561514},
doi = {10.1145/3561514},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChoiSSDC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CortsA23,
author = {Reinout Corts and
Nikolaos Alachiotis},
title = {A Survey of Processing Systems for Phylogenetics and Population Genetics},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {35:1--35:27},
year = {2023},
url = {https://doi.org/10.1145/3588033},
doi = {10.1145/3588033},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CortsA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FiegeZ23,
author = {Nicolai Fiege and
Peter Zipf},
title = {{BLOOP:} Boolean Satisfiability-based Optimized Loop Pipelining},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {49:1--49:32},
year = {2023},
url = {https://doi.org/10.1145/3599972},
doi = {10.1145/3599972},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/FiegeZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GanewatthaKLL23,
author = {Chanaka Ganewattha and
Zaheer Khan and
Janne Lehtom{\"{a}}ki and
Matti Latva{-}aho},
title = {Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning
on Wireless {RF} Data},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {19:1--19:29},
year = {2023},
url = {https://doi.org/10.1145/3563394},
doi = {10.1145/3563394},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GanewatthaKLL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GaoWS23,
author = {Yizhao Gao and
Song Wang and
Hayden Kwok{-}Hay So},
title = {A Reconfigurable Architecture for Real-time Event-based Multi-Object
Tracking},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {58:1--58:26},
year = {2023},
url = {https://doi.org/10.1145/3593587},
doi = {10.1145/3593587},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GaoWS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GebauerKGS23,
author = {Richard Gebauer and
Nick Karcher and
Mehmed G{\"{u}}ler and
Oliver Sander},
title = {QiCells: {A} Modular RFSoC-based Approach to Interface Superconducting
Quantum Bits},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {32:1--32:23},
year = {2023},
url = {https://doi.org/10.1145/3571820},
doi = {10.1145/3571820},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GebauerKGS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GeethakumariS23,
author = {Prajith Ramakrishnan Geethakumari and
Ioannis Sourdis},
title = {Stream Aggregation with Compressed Sliding Windows},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {37:1--37:28},
year = {2023},
url = {https://doi.org/10.1145/3590774},
doi = {10.1145/3590774},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GeethakumariS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GiechaskielTS23,
author = {Ilias Giechaskiel and
Shanquan Tian and
Jakub Szefer},
title = {Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {6:1--6:29},
year = {2023},
url = {https://doi.org/10.1145/3534972},
doi = {10.1145/3534972},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GiechaskielTS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuoCLSTKQWUFZC23,
author = {Licheng Guo and
Yuze Chi and
Jason Lau and
Linghao Song and
Xingyu Tian and
Moazin Khatti and
Weikang Qiao and
Jie Wang and
Ecenur Ustun and
Zhenman Fang and
Zhiru Zhang and
Jason Cong},
title = {{TAPA:} {A} Scalable Task-parallel Dataflow Programming Framework
for Modern FPGAs with Co-optimization of {HLS} and Physical Design},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {63:1--63:31},
year = {2023},
url = {https://doi.org/10.1145/3609335},
doi = {10.1145/3609335},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GuoCLSTKQWUFZC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuoMZLHLLQCSXKZC23,
author = {Licheng Guo and
Pongstorn Maidee and
Yun Zhou and
Chris Lavin and
Eddie Hung and
Wuxi Li and
Jason Lau and
Weikang Qiao and
Yuze Chi and
Linghao Song and
Yuanlong Xiao and
Alireza Kaviani and
Zhiru Zhang and
Jason Cong},
title = {RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive
{FPGA} Designs Through Partial Reconfiguration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {59:1--59:30},
year = {2023},
url = {https://doi.org/10.1145/3593025},
doi = {10.1145/3593025},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GuoMZLHLLQCSXKZC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HeBXA23,
author = {Pengzhou He and
Tianyou Bao and
Jiafeng Xie and
Moeness G. Amin},
title = {{FPGA} Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based
Post-quantum Cryptography},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {45:1--45:23},
year = {2023},
url = {https://doi.org/10.1145/3569457},
doi = {10.1145/3569457},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HeBXA23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Ienne23,
author = {Paolo Ienne},
title = {Introduction to the Special Section on {FPGA} 2022},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {56:1--56:2},
year = {2023},
url = {https://doi.org/10.1145/3618114},
doi = {10.1145/3618114},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/Ienne23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/IoannouF23,
author = {Lenos Ioannou and
Suhaib A. Fahmy},
title = {Streaming Overlay Architecture for Lightweight {LSTM} Computation
on {FPGA} SoCs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {8:1--8:26},
year = {2023},
url = {https://doi.org/10.1145/3543069},
doi = {10.1145/3543069},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/IoannouF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/IskandarGG23,
author = {Veronia Iskandar and
Mohamed A. Abd El Ghany and
Diana G{\"{o}}hringer},
title = {Near-memory Computing on FPGAs with 3D-stacked Memories: Applications,
Architectures, and Optimizations},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {16:1--16:32},
year = {2023},
url = {https://doi.org/10.1145/3547658},
doi = {10.1145/3547658},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/IskandarGG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JosipovicMGI23,
author = {Lana Josipovic and
Axel Marmet and
Andrea Guerrieri and
Paolo Ienne},
title = {Resource Sharing in Dataflow Circuits},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {54:1--54:27},
year = {2023},
url = {https://doi.org/10.1145/3597614},
doi = {10.1145/3597614},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/JosipovicMGI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JunYJC23,
author = {HyeGang Jun and
Hanchen Ye and
Hyunmin Jeong and
Deming Chen},
title = {AutoScaleDSE: {A} Scalable Design Space Exploration Engine for High-Level
Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {46:1--46:30},
year = {2023},
url = {https://doi.org/10.1145/3572959},
doi = {10.1145/3572959},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JunYJC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KalantarZB23,
author = {Amin Kalantar and
Zachary Zimmerman and
Philip Brisk},
title = {FPGA-based Acceleration of Time Series Similarity Prediction: From
Cloud to Edge},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {12:1--12:27},
year = {2023},
url = {https://doi.org/10.1145/3555810},
doi = {10.1145/3555810},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KalantarZB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KarakchiB23,
author = {Rasha Karakchi and
Jason D. Bakos},
title = {{NAPOLY:} {A} Non-deterministic Automata Processor OverLaY},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {38:1--38:25},
year = {2023},
url = {https://doi.org/10.1145/3593586},
doi = {10.1145/3593586},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KarakchiB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KochZ23,
author = {Andreas Koch and
Wei Zhang},
title = {Introduction to the Special Issue on {FPT} 2021},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {30:1--30:2},
year = {2023},
url = {https://doi.org/10.1145/3603701},
doi = {10.1145/3603701},
timestamp = {Sun, 26 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KochZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Leeser23,
author = {Miriam Leeser},
title = {Artifact Evaluation for {ACM} {TRETS} Papers Submitted from the {FPT}
Journal Track},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {40:1--40:2},
year = {2023},
url = {https://doi.org/10.1145/3596513},
doi = {10.1145/3596513},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Leeser23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LeipnitzN23,
author = {Marcos T. Leipnitz and
Gabriel L. Nazar},
title = {Constraint-Aware Multi-Technique Approximate High-Level Synthesis
for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {61:1--61:28},
year = {2023},
url = {https://doi.org/10.1145/3624481},
doi = {10.1145/3624481},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LeipnitzN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiH23,
author = {Jing Li and
Martin C. Herbordt},
title = {Introduction to the Special Section on {FCCM} 2022},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {51:1--51:2},
year = {2023},
url = {https://doi.org/10.1145/3632092},
doi = {10.1145/3632092},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiLLJBL23,
author = {Carol Jingyi Li and
Xiangwei Li and
Binglei Lou and
Craig T. Jin and
David Boland and
Philip H. W. Leong},
title = {Fixed-point {FPGA} Implementation of the {FFT} Accumulation Method
for Real-time Cyclostationary Analysis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {41:1--41:28},
year = {2023},
url = {https://doi.org/10.1145/3567429},
doi = {10.1145/3567429},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiLLJBL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiMLLB23,
author = {Xiangwei Li and
Douglas L. Maskell and
Carol Jingyi Li and
Philip H. W. Leong and
David Boland},
title = {A Scalable Systolic Accelerator for Estimation of the Spectral Correlation
Density Function and Its {FPGA} Implementation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {9:1--9:24},
year = {2023},
url = {https://doi.org/10.1145/3546181},
doi = {10.1145/3546181},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiMLLB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiSPTH23,
author = {Xiang Li and
Peter Stanwicks and
George Provelengios and
Russell Tessier and
Daniel E. Holcomb},
title = {Jitter-based Adaptive True Random Number Generation Circuits for FPGAs
in the Cloud},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {3:1--3:20},
year = {2023},
url = {https://doi.org/10.1145/3487554},
doi = {10.1145/3487554},
timestamp = {Thu, 16 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiSPTH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuLSFG23,
author = {Kenneth Liu and
Alec Lu and
Kartik Samtani and
Zhenman Fang and
Licheng Guo},
title = {CHIP-KNNv2: {A} Configurable and High-Performance K-Nearest Neighbors
Accelerator on HBM-based FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {62:1--62:26},
year = {2023},
url = {https://doi.org/10.1145/3616873},
doi = {10.1145/3616873},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuLSFG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LouBL23,
author = {Binglei Lou and
David Boland and
Philip H. W. Leong},
title = {fSEAD: {A} Composable FPGA-based Streaming Ensemble Anomaly Detection
Library},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {42:1--42:27},
year = {2023},
url = {https://doi.org/10.1145/3568992},
doi = {10.1145/3568992},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LouBL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuYHLYHMCY23,
author = {Yingchun Lu and
Yun Yang and
Rong Hu and
Huaguo Liang and
Maoxiang Yi and
Zhengfeng Huang and
Yuanming Ma and
Tian Chen and
Liang Yao},
title = {High-efficiency {TRNG} Design Based on Multi-bit Dual-ring Oscillator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {64:1--64:23},
year = {2023},
url = {https://doi.org/10.1145/3624991},
doi = {10.1145/3624991},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LuYHLYHMCY23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MM23,
author = {Dhayalakumar M and
Sk. Noor Mahammad},
title = {Deterministic Approach for Range-enhanced Reconfigurable Packet Classification
Engine},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {29:1--29:26},
year = {2023},
url = {https://doi.org/10.1145/3586577},
doi = {10.1145/3586577},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MachadoFOM23,
author = {Pedro Machado and
Jo{\~{a}}o Filipe Ferreira and
Andreas Oikonomou and
T. M. McGinnity},
title = {NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {36:1--36:23},
year = {2023},
url = {https://doi.org/10.1145/3588318},
doi = {10.1145/3588318},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MachadoFOM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MaoCLDSKC23,
author = {Gaoyu Mao and
Donglong Chen and
Guangyan Li and
Wangchen Dai and
Abdurrashid Ibrahim Sanka and
{\c{C}}etin Kaya Ko{\c{c}} and
Ray C. C. Cheung},
title = {High-performance and Configurable {SW/HW} Co-design of Post-quantum
Signature CRYSTALS-Dilithium},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {44:1--44:28},
year = {2023},
url = {https://doi.org/10.1145/3569456},
doi = {10.1145/3569456},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MaoCLDSKC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MeyerKP23,
author = {Marius Meyer and
Tobias Kenter and
Christian Plessl},
title = {Multi-FPGA Designs and Scaling of {HPC} Challenge Benchmarks via {MPI}
and Circuit-switched Inter-FPGA Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {24:1--24:27},
year = {2023},
url = {https://doi.org/10.1145/3576200},
doi = {10.1145/3576200},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MeyerKP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MoiniDLPBTH23,
author = {Shayan Moini and
Aleksa Deric and
Xiang Li and
George Provelengios and
Wayne P. Burleson and
Russell Tessier and
Daniel E. Holcomb},
title = {Voltage Sensor Implementations for Remote Power Attacks on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {11:1--11:21},
year = {2023},
url = {https://doi.org/10.1145/3555048},
doi = {10.1145/3555048},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MoiniDLPBTH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MouraLC23,
author = {Rafael F{\~{a}}o de Moura and
Jo{\~{a}}o Paulo Cardoso de Lima and
Luigi Carro},
title = {Data and Computation Reuse in CNNs Using Memristor TCAMs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {14:1--14:24},
year = {2023},
url = {https://doi.org/10.1145/3549536},
doi = {10.1145/3549536},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MouraLC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NayakZSCMTRBHHR23,
author = {Ankita Nayak and
Keyi Zhang and
Rajsekhar Setaluri and
Alex Carsello and
Makai Mann and
Christopher Torng and
Stephen Richardson and
Rick Bahr and
Pat Hanrahan and
Mark Horowitz and
Priyanka Raina},
title = {Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained
Power Domains},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {26:1--26:28},
year = {2023},
url = {https://doi.org/10.1145/3558394},
doi = {10.1145/3558394},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NayakZSCMTRBHHR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NechiGMMBB23,
author = {Anouar Nechi and
Lukas Groth and
Saleh Mulhem and
Farhad Merchant and
Rainer Buchty and
Mladen Berekovic},
title = {FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {60:1--60:32},
year = {2023},
url = {https://doi.org/10.1145/3613963},
doi = {10.1145/3613963},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/NechiGMMBB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ProulxCFM23,
author = {Alexandre Proulx and
Jean{-}Yves Chouinard and
Paul Fortier and
Amine Miled},
title = {A Survey on {FPGA} Cybersecurity Design Strategies},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {20:1--20:33},
year = {2023},
url = {https://doi.org/10.1145/3561515},
doi = {10.1145/3561515},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ProulxCFM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/QueNFLMTNNL23,
author = {Zhiqiang Que and
Hiroki Nakahara and
Hongxiang Fan and
He Li and
Jiuxi Meng and
Kuen Hung Tsoi and
Xinyu Niu and
Eriko Nurvitadhi and
Wayne Luk},
title = {Remarn: {A} Reconfigurable Multi-threaded Multi-core Accelerator for
Recurrent Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {4:1--4:26},
year = {2023},
url = {https://doi.org/10.1145/3534969},
doi = {10.1145/3534969},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/QueNFLMTNNL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RautKV23,
author = {Gopal Raut and
Saurabh Karkun and
Santosh Kumar Vishvakarma},
title = {An Empirical Approach to Enhance Performance for Scalable CORDIC-Based
Deep Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {39:1--39:32},
year = {2023},
url = {https://doi.org/10.1145/3596220},
doi = {10.1145/3596220},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RautKV23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ScheltenSKSS23,
author = {Niklas Schelten and
Fritjof Steinert and
Justin Knapheide and
Anton Schulte and
Benno Stabernack},
title = {A High-Throughput, Resource-Efficient Implementation of the RoCEv2
Remote {DMA} Protocol and its Application},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {5:1--5:23},
year = {2023},
url = {https://doi.org/10.1145/3543176},
doi = {10.1145/3543176},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ScheltenSKSS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShahsavaniFNP23,
author = {Soheil Nazar Shahsavani and
Arash Fayyazi and
Mahdi Nazemi and
Massoud Pedram},
title = {Efficient Compilation and Mapping of Fixed Function Combinational
Logic onto Digital Signal Processors Targeting Neural Network Inference
and Utilizing High-level Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {17:1--17:25},
year = {2023},
url = {https://doi.org/10.1145/3559543},
doi = {10.1145/3559543},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ShahsavaniFNP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShiCYXLHW23,
author = {Zhengyuan Shi and
Cheng Chen and
Gangqiang Yang and
Hailiang Xiong and
Fudong Li and
Honggang Hu and
Zhiguo Wan},
title = {Design Space Exploration of Galois and Fibonacci Configuration Based
on Espresso Stream Cipher},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {43:1--43:24},
year = {2023},
url = {https://doi.org/10.1145/3567428},
doi = {10.1145/3567428},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ShiCYXLHW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShiZZW23,
author = {Kaichuang Shi and
Xuegong Zhou and
Hao Zhou and
Lingli Wang},
title = {An Optimized {GIB} Routing Architecture with Bent Wires for {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {2:1--2:28},
year = {2023},
url = {https://doi.org/10.1145/3519599},
doi = {10.1145/3519599},
timestamp = {Tue, 02 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ShiZZW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SinnenLD23,
author = {Oliver Sinnen and
Qiang Liu and
Azadeh Davoodi},
title = {Introduction to Special Section on FPT'20},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {1:1--1:2},
year = {2023},
url = {https://doi.org/10.1145/3579850},
doi = {10.1145/3579850},
timestamp = {Thu, 16 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/SinnenLD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SkubichRR23,
author = {Christian Skubich and
Peter Reichel and
Marc Reichenbach},
title = {Increasing the Robustness of TERO-TRNGs Against Process Variation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {3},
pages = {48:1--48:29},
year = {2023},
url = {https://doi.org/10.1145/3597418},
doi = {10.1145/3597418},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SkubichRR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SoldaviniFTHCP23,
author = {Stephanie Soldavini and
Karl F. A. Friebel and
Mattia Tibaldi and
Gerald Hempel and
Jer{\'{o}}nimo Castrill{\'{o}}n and
Christian Pilato},
title = {Automatic Creation of High-bandwidth Memory Architectures from Domain-specific
Languages: The Case of Computational Fluid Dynamics},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {21:1--21:34},
year = {2023},
url = {https://doi.org/10.1145/3563553},
doi = {10.1145/3563553},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SoldaviniFTHCP23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SuhMNKCS23,
author = {Han{-}Sok Suh and
Jian Meng and
Ty Nguyen and
Vijay Kumar and
Yu Cao and
Jae{-}Sun Seo},
title = {Algorithm-hardware Co-optimization for Energy-efficient Drone Detection
on Resource-constrained {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {33:1--33:25},
year = {2023},
url = {https://doi.org/10.1145/3583074},
doi = {10.1145/3583074},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SuhMNKCS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TaoWLWH23,
author = {Zhuofu Tao and
Chen Wu and
Yuan Liang and
Kun Wang and
Lei He},
title = {{LW-GCN:} {A} Lightweight FPGA-based Graph Convolutional Network Accelerator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {10:1--10:19},
year = {2023},
url = {https://doi.org/10.1145/3550075},
doi = {10.1145/3550075},
timestamp = {Wed, 02 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TaoWLWH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TianYLGCF23,
author = {Xingyu Tian and
Zhifan Ye and
Alec Lu and
Licheng Guo and
Yuze Chi and
Zhenman Fang},
title = {{SASA:} {A} Scalable and Automatic Stencil Acceleration Framework
for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {28:1--28:33},
year = {2023},
url = {https://doi.org/10.1145/3572547},
doi = {10.1145/3572547},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TianYLGCF23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/UenoS23,
author = {Tomohiro Ueno and
Kentaro Sano},
title = {{VCSN:} Virtual Circuit-Switching Network for Flexible and Simple-to-Operate
Communication in {HPC} {FPGA} Cluster},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {25:1--25:32},
year = {2023},
url = {https://doi.org/10.1145/3579848},
doi = {10.1145/3579848},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/UenoS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/VestiasDSN23,
author = {M{\'{a}}rio P. V{\'{e}}stias and
Rui Policarpo Duarte and
Jos{\'{e}} T. de Sousa and
Hor{\'{a}}cio C. Neto},
title = {Efficient Design of Low Bitwidth Convolutional Neural Networks on
{FPGA} with Optimized Dot Product Units},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {13:1--13:36},
year = {2023},
url = {https://doi.org/10.1145/3546182},
doi = {10.1145/3546182},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/VestiasDSN23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WangASCCAD23,
author = {Erwei Wang and
Marie Auffret and
Georgios{-}Ilias Stavrou and
Peter Y. K. Cheung and
George A. Constantinides and
Mohamed S. Abdelfattah and
James J. Davis},
title = {Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based
Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {57:1--57:25},
year = {2023},
url = {https://doi.org/10.1145/3583075},
doi = {10.1145/3583075},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WangASCCAD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WolfSDH23,
author = {Dennis Leander Wolf and
Christoph Spang and
Daniel Diener and
Christian Hochberger},
title = {Advantages of a Statistical Estimation Approach for Clock Frequency
Estimation of Heterogeneous and Irregular CGRAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {1},
pages = {7:1--7:33},
year = {2023},
url = {https://doi.org/10.1145/3531062},
doi = {10.1145/3531062},
timestamp = {Tue, 28 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WolfSDH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WuHJZZZZWYZ23,
author = {Guiming Wu and
Qianwen He and
Jiali Jiang and
Zhenxiang Zhang and
Yuan Zhao and
Yinchao Zou and
Jie Zhang and
Changzheng Wei and
Ying Yan and
Hui Zhang},
title = {Topgun: An {ECC} Accelerator for Private Set Intersection},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {52:1--52:30},
year = {2023},
url = {https://doi.org/10.1145/3603114},
doi = {10.1145/3603114},
timestamp = {Fri, 19 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WuHJZZZZWYZ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/XuRC23,
author = {Tiancheng Xu and
Scott Rixner and
Alan L. Cox},
title = {An {FPGA} Accelerator for Genome Variant Calling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {4},
pages = {53:1--53:29},
year = {2023},
url = {https://doi.org/10.1145/3595297},
doi = {10.1145/3595297},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/XuRC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YangSCXLHW23,
author = {Gangqiang Yang and
Zhengyuan Shi and
Cheng Chen and
Hailiang Xiong and
Fudong Li and
Honggang Hu and
Zhiguo Wan},
title = {Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {22:1--22:32},
year = {2023},
url = {https://doi.org/10.1145/3569455},
doi = {10.1145/3569455},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YangSCXLHW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhaoMHZXB23,
author = {Kang Zhao and
Yuchun Ma and
Ruining He and
Jixing Zhang and
Ning Xu and
Jinian Bian},
title = {Adaptive Selection and Clustering of Partial Reconfiguration Modules
for Modern {FPGA} Design Flow},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {16},
number = {2},
pages = {27:1--27:24},
year = {2023},
url = {https://doi.org/10.1145/3567427},
doi = {10.1145/3567427},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhaoMHZXB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AlachiotisSPP22,
author = {Nikolaos Alachiotis and
Panagiotis Skrimponis and
Manolis Pissadakis and
Dionisios N. Pnevmatikatos},
title = {Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {25:1--25:32},
year = {2022},
url = {https://doi.org/10.1145/3484983},
doi = {10.1145/3484983},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/AlachiotisSPP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AlonsoPRPUSKBV22,
author = {Tobias Alonso and
Lucian Petrica and
Mario Ruiz and
Jakoba Petri{-}Koenig and
Yaman Umuroglu and
Ioannis Stamelos and
Elias Koromilas and
Michaela Blott and
Kees A. Vissers},
title = {Elastic-DF: Scaling Performance of {DNN} Inference in {FPGA} Clouds
through Automatic Partitioning},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {15:1--15:34},
year = {2022},
url = {https://doi.org/10.1145/3470567},
doi = {10.1145/3470567},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AlonsoPRPUSKBV22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AroraGMBJ22,
author = {Aman Arora and
Moinak Ghosh and
Samidh Mehta and
Vaughn Betz and
Lizy K. John},
title = {Tensor Slices: {FPGA} Building Blocks For The Deep Learning Era},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {46:1--46:34},
year = {2022},
url = {https://doi.org/10.1145/3529650},
doi = {10.1145/3529650},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AroraGMBJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AsiaticiI22,
author = {Mikhail Asiatici and
Paolo Ienne},
title = {Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems
for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {13:1--13:33},
year = {2022},
url = {https://doi.org/10.1145/3466823},
doi = {10.1145/3466823},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AsiaticiI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BobdaMCETVEKHLH22,
author = {Christophe Bobda and
Joel Mandebi Mbongue and
Paul Chow and
Mohammad Ewais and
Naif Tarafdar and
Juan Camilo Vega and
Ken Eguro and
Dirk Koch and
Suranga Handagala and
Miriam Leeser and
Martin C. Herbordt and
Hafsah Shahzad and
H. Peter Hofstee and
Burkhard Ringlein and
Jakub Szefer and
Ahmed Sanaullah and
Russell Tessier},
title = {The Future of {FPGA} Acceleration in Datacenters and the Cloud},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {34:1--34:42},
year = {2022},
url = {https://doi.org/10.1145/3506713},
doi = {10.1145/3506713},
timestamp = {Tue, 19 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/BobdaMCETVEKHLH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BrennsteinerATM22,
author = {Stefan Brennsteiner and
Tughrul Arslan and
John Thompson and
Andrew C. McCormick},
title = {A Real-Time Deep Learning {OFDM} Receiver},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {26:1--26:25},
year = {2022},
url = {https://doi.org/10.1145/3494049},
doi = {10.1145/3494049},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BrennsteinerATM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CahillHG22,
author = {Eli Cahill and
Brad L. Hutchings and
Jeffrey Goeders},
title = {Approaches for {FPGA} Design Assurance},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {28:1--28:29},
year = {2022},
url = {https://doi.org/10.1145/3491233},
doi = {10.1145/3491233},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CahillHG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Chen22,
author = {Deming Chen},
title = {Note from the {TRETS} EiC about the new Journal-first track in FPT'21},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {7e:1},
year = {2022},
url = {https://doi.org/10.1145/3501280},
doi = {10.1145/3501280},
timestamp = {Fri, 11 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/Chen22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenCTCHWC22,
author = {Xinyu Chen and
Feng Cheng and
Hongshi Tan and
Yao Chen and
Bingsheng He and
Weng{-}Fai Wong and
Deming Chen},
title = {ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs
with {HLS}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {44:1--44:31},
year = {2022},
url = {https://doi.org/10.1145/3517141},
doi = {10.1145/3517141},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChenCTCHWC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CongLLNPVZ22,
author = {Jason Cong and
Jason Lau and
Gai Liu and
Stephen Neuendorffer and
Peichen Pan and
Kees A. Vissers and
Zhiru Zhang},
title = {{FPGA} {HLS} Today: Successes, Challenges, and Opportunities},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {51:1--51:42},
year = {2022},
url = {https://doi.org/10.1145/3530775},
doi = {10.1145/3530775},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/CongLLNPVZ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CookAGGGH22,
author = {Hayden Cook and
Jacob Arscott and
Brent George and
Tanner Gaskin and
Jeffrey Goeders and
Brad L. Hutchings},
title = {Inducing Non-uniform {FPGA} Aging Using Configuration-based Short
Circuits},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {41:1--41:33},
year = {2022},
url = {https://doi.org/10.1145/3517042},
doi = {10.1145/3517042},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/CookAGGGH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DAlbertoWNNDS22,
author = {Paolo D'Alberto and
Victor Wu and
Aaron Ng and
Rahul Nimaiyar and
Elliott Delaye and
Ashish Sirasao},
title = {xDNN: Inference for Deep Convolutional Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {18:1--18:29},
year = {2022},
url = {https://doi.org/10.1145/3473334},
doi = {10.1145/3473334},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DAlbertoWNNDS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DamianiFBBS22,
author = {Andrea Damiani and
Giorgia Fiscaletti and
Marco Bacis and
Rolando Brondolin and
Marco D. Santambrogio},
title = {BlastFunction: {A} Full-stack Framework Bringing {FPGA} Hardware Acceleration
to Cloud-native Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {17:1--17:27},
year = {2022},
url = {https://doi.org/10.1145/3472958},
doi = {10.1145/3472958},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DamianiFBBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DewaldRHM22,
author = {Florian Dewald and
Johanna Rohde and
Christian Hochberger and
Heiko Mantel},
title = {Improving Loop Parallelization by a Combination of Static and Dynamic
Analyses in {HLS}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {31:1--31:31},
year = {2022},
url = {https://doi.org/10.1145/3501801},
doi = {10.1145/3501801},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DewaldRHM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DoganE22,
author = {Atakan Dogan and
Kemal Ebcioglu},
title = {Cloud Building Block Chip for Creating {FPGA} and {ASIC} Clouds},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {14:1--14:35},
year = {2022},
url = {https://doi.org/10.1145/3466822},
doi = {10.1145/3466822},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DoganE22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DuCLTZWZYW22,
author = {Gaoming Du and
Bangyi Chen and
Zhenmin Li and
Zhenxing Tu and
Junjie Zhou and
Shenya Wang and
Qinghao Zhao and
Yongsheng Yin and
Xiaolei Wang},
title = {A {BNN} Accelerator Based on Edge-skip-calculation Strategy and Consolidation
Compressed Tree},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {30:1--30:20},
year = {2022},
url = {https://doi.org/10.1145/3494569},
doi = {10.1145/3494569},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DuCLTZWZYW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/EbciogluS22,
author = {Kemal Ebcioglu and
Ismail San},
title = {Highly Parallel Multi-FPGA System Compilation from Sequential {C/C++}
Code in the {AWS} Cloud},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {47:1--47:42},
year = {2022},
url = {https://doi.org/10.1145/3507698},
doi = {10.1145/3507698},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/EbciogluS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/EguroNPR22,
author = {Ken Eguro and
Stephen Neuendorffer and
Viktor K. Prasanna and
Hongbo Rong},
title = {Introduction to Special Issue on FPGAs in Data Centers},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {11:1--11:2},
year = {2022},
url = {https://doi.org/10.1145/3493607},
doi = {10.1145/3493607},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/EguroNPR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/EguroNPR22a,
author = {Ken Eguro and
Stephen Neuendorffer and
Viktor K. Prasanna and
Hongbo Rong},
title = {Introduction to Special Issue on FPGAs in Data Centers, Part {II}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {22:1--22:2},
year = {2022},
url = {https://doi.org/10.1145/3495231},
doi = {10.1145/3495231},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/EguroNPR22a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FarajiAB22,
author = {S. Rasoul Faraji and
Pierre Abillama and
Kia Bazargan},
title = {Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary
Computing for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {29:1--29:25},
year = {2022},
url = {https://doi.org/10.1145/3494570},
doi = {10.1145/3494570},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/FarajiAB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GibsonRNW22,
author = {Kahlan Gibson and
Esther Roorda and
Daniel Holanda Noronha and
Steven J. E. Wilton},
title = {Adaptive Clock Management of HLS-generated Circuits on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {49:1--49:32},
year = {2022},
url = {https://doi.org/10.1145/3520140},
doi = {10.1145/3520140},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GibsonRNW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GrossHWS22,
author = {Mathieu Gross and
Konrad Hohentanner and
Stefan Wiehler and
Georg Sigl},
title = {Enhancing the Security of FPGA-SoCs via the Usage of {ARM} TrustZone
and a Hybrid-TPM},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {5:1--5:26},
year = {2022},
url = {https://doi.org/10.1145/3472959},
doi = {10.1145/3472959},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GrossHWS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HogervorstNMQBR22,
author = {Tom Hogervorst and
Razvan Nane and
Giacomo Marchiori and
Tong Dong Qiu and
Markus Blatt and
Alf Birger Rustad},
title = {Hardware Acceleration of High-Performance Computational Flow Dynamics
Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {20:1--20:35},
year = {2022},
url = {https://doi.org/10.1145/3476229},
doi = {10.1145/3476229},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HogervorstNMQBR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JosipovicSGIC22,
author = {Lana Josipovic and
Shabnam Sheikhha and
Andrea Guerrieri and
Paolo Ienne and
Jordi Cortadella},
title = {Buffer Placement and Sizing for High-Performance Dataflow Circuits},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {4:1--4:32},
year = {2022},
url = {https://doi.org/10.1145/3477053},
doi = {10.1145/3477053},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JosipovicSGIC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KellerW22,
author = {Andrew M. Keller and
Michael J. Wirthlin},
title = {The Impact of Terrestrial Radiation on FPGAs in Data Centers},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {12:1--12:21},
year = {2022},
url = {https://doi.org/10.1145/3457198},
doi = {10.1145/3457198},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KellerW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LanghammerNGP22,
author = {Martin Langhammer and
Eriko Nurvitadhi and
Sergey Gribok and
Bogdan Pasca},
title = {Stratix 10 {NX} Architecture},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {45:1--45:32},
year = {2022},
url = {https://doi.org/10.1145/3520197},
doi = {10.1145/3520197},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LanghammerNGP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Leong22,
author = {Philip H. W. Leong},
title = {Introduction to Special Section on {FPGA} 2021},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {42:1},
year = {2022},
url = {https://doi.org/10.1145/3536335},
doi = {10.1145/3536335},
timestamp = {Thu, 05 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/Leong22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LienenP22,
author = {Christian Lienen and
Marco Platzner},
title = {Design of Distributed Reconfigurable Robotics Systems with ReconROS},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {27:1--27:20},
year = {2022},
url = {https://doi.org/10.1145/3494571},
doi = {10.1145/3494571},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LienenP22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuFS22,
author = {Alec Lu and
Zhenman Fang and
Lesley Shannon},
title = {Demystifying the Soft and Hardened Memory Systems of Modern FPGAs
for Software Programmers through Microbenchmarking},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {43:1--43:33},
year = {2022},
url = {https://doi.org/10.1145/3517131},
doi = {10.1145/3517131},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LuFS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MalikLPK22,
author = {Gurshaant Malik and
Ian Elmor Lang and
Rodolfo Pellizzoni and
Nachiket Kapre},
title = {HopliteML: Evolving Application Customized {FPGA} NoCs with Adaptable
Routers and Regulators},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {40:1--40:33},
year = {2022},
url = {https://doi.org/10.1145/3507699},
doi = {10.1145/3507699},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MalikLPK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MatthewsLFS22,
author = {Eric Matthews and
Alec Lu and
Zhenman Fang and
Lesley Shannon},
title = {Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {32:1--32:27},
year = {2022},
url = {https://doi.org/10.1145/3502492},
doi = {10.1145/3502492},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MatthewsLFS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MbongueKSB22,
author = {Joel Mandebi Mbongue and
Danielle Tchuinkou Kwadjo and
Alex Shuping and
Christophe Bobda},
title = {Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {19:1--19:31},
year = {2022},
url = {https://doi.org/10.1145/3474058},
doi = {10.1145/3474058},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MbongueKSB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MentensST22,
author = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso},
title = {Introduction to the Special Section on {FPL} 2020},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {35:1--35:2},
year = {2022},
url = {https://doi.org/10.1145/3536336},
doi = {10.1145/3536336},
timestamp = {Fri, 15 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MentensST22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MenzelPK22,
author = {Johannes Menzel and
Christian Plessl and
Tobias Kenter},
title = {The Strong Scaling Advantage of FPGAs in {HPC} for N-body Simulations},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {10:1--10:30},
year = {2022},
url = {https://doi.org/10.1145/3491235},
doi = {10.1145/3491235},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MenzelPK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NikolicZI22,
author = {Stefan Nikolic and
Grace Zgheib and
Paolo Ienne},
title = {Detailed Placement for Dedicated LUT-Level {FPGA} Interconnect},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {37:1--37:33},
year = {2022},
url = {https://doi.org/10.1145/3501802},
doi = {10.1145/3501802},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/NikolicZI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PanchapakesanFL22,
author = {Sathish Panchapakesan and
Zhenman Fang and
Jian Li},
title = {SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {48:1--48:27},
year = {2022},
url = {https://doi.org/10.1145/3514253},
doi = {10.1145/3514253},
timestamp = {Sun, 23 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PanchapakesanFL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PapaphilippouMG22,
author = {Philippos Papaphilippou and
Jiuxi Meng and
Nadeen Gebara and
Wayne Luk},
title = {Hipernetch: High-Performance {FPGA} Network Switch},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {3:1--3:31},
year = {2022},
url = {https://doi.org/10.1145/3477054},
doi = {10.1145/3477054},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PapaphilippouMG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RasoulinezhadRW22,
author = {Seyedramin Rasoulinezhad and
Esther Roorda and
Steve Wilton and
Philip H. W. Leong and
David Boland},
title = {Rethinking Embedded Blocks for Machine Learning Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {9:1--9:30},
year = {2022},
url = {https://doi.org/10.1145/3491234},
doi = {10.1145/3491234},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RasoulinezhadRW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RoordaRLW22,
author = {Esther Roorda and
Seyedramin Rasoulinezhad and
Philip H. W. Leong and
Steven J. E. Wilton},
title = {{FPGA} Architecture Exploration for {DNN} Acceleration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {33:1--33:37},
year = {2022},
url = {https://doi.org/10.1145/3503465},
doi = {10.1145/3503465},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RoordaRLW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RybalkinNTW22,
author = {Vladimir Rybalkin and
Jonas Ney and
Menbere Kina Tekleyohannes and
Norbert Wehn},
title = {When Massive {GPU} Parallelism Ain't Enough: {A} Novel Hardware Architecture
of 2D-LSTM Neural Network},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {2:1--2:35},
year = {2022},
url = {https://doi.org/10.1145/3469661},
doi = {10.1145/3469661},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RybalkinNTW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SalamatZKR22,
author = {Sahand Salamat and
Hui Zhang and
Yang{-}Seok Ki and
Tajana Rosing},
title = {{NASCENT2:} Generic Near-Storage Sort Accelerator for Data Analytics
on SmartSSD},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {16:1--16:29},
year = {2022},
url = {https://doi.org/10.1145/3472769},
doi = {10.1145/3472769},
timestamp = {Wed, 06 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SalamatZKR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Shannon22,
author = {Lesley Shannon},
title = {Introduction to Special Section on {FPGA} 2020},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {1:1--1:2},
year = {2022},
url = {https://doi.org/10.1145/3485586},
doi = {10.1145/3485586},
timestamp = {Fri, 11 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/Shannon22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SherwinWTSS22,
author = {Krystine Dawn Sherwin and
Kevin I{-}Kai Wang and
Prabu Thiagaraj and
Ben Stappers and
Oliver Sinnen},
title = {Median Filters on FPGAs for Infinite Data and Large, Rectangular Windows},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {50:1--50:24},
year = {2022},
url = {https://doi.org/10.1145/3530273},
doi = {10.1145/3530273},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/SherwinWTSS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShiKHDSA22,
author = {Runbin Shi and
Kaan Kara and
Christoph Hagleitner and
Dionysios Diamantopoulos and
Dimitris Syrivelis and
Gustavo Alonso},
title = {Exploiting {HBM} on FPGAs for Data Processing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {36:1--36:27},
year = {2022},
url = {https://doi.org/10.1145/3491238},
doi = {10.1145/3491238},
timestamp = {Thu, 05 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ShiKHDSA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SinghDGHSCM22,
author = {Gagandeep Singh and
Dionysios Diamantopoulos and
Juan G{\'{o}}mez{-}Luna and
Christoph Hagleitner and
Sander Stuijk and
Henk Corporaal and
Onur Mutlu},
title = {Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {39:1--39:27},
year = {2022},
url = {https://doi.org/10.1145/3501804},
doi = {10.1145/3501804},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SinghDGHSCM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/StreitKBWT22,
author = {Franz{-}Josef Streit and
Paul Kr{\"{u}}ger and
Andreas Becher and
Stefan Wildermann and
J{\"{u}}rgen Teich},
title = {Design and Evaluation of a Tunable {PUF} Architecture for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {7:1--7:27},
year = {2022},
url = {https://doi.org/10.1145/3491237},
doi = {10.1145/3491237},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/StreitKBWT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SunKJ22,
author = {Gongjin Sun and
Seongyoung Kang and
Sang{-}Woo Jun},
title = {BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing
Accelerators via Accelerated Compression},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {2},
pages = {21:1--21:34},
year = {2022},
url = {https://doi.org/10.1145/3476831},
doi = {10.1145/3476831},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/SunKJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TarafdarGHKLRTW22,
author = {Naif Tarafdar and
Giuseppe Di Guglielmo and
Philip C. Harris and
Jeffrey D. Krupa and
Vladimir Loncar and
Dylan S. Rankin and
Nhan Tran and
Zhenbin Wu and
Qianfeng Shen and
Paul Chow},
title = {\emph{AIgean}: An Open Framework for Deploying Machine Learning on
Heterogeneous Clusters},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {23:1--23:32},
year = {2022},
url = {https://doi.org/10.1145/3482854},
doi = {10.1145/3482854},
timestamp = {Mon, 25 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TarafdarGHKLRTW22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WuWCWH22,
author = {Chen Wu and
Mingyu Wang and
Xinyuan Chu and
Kun Wang and
Lei He},
title = {Low-precision Floating-point Arithmetic for High-performance FPGA-based
{CNN} Acceleration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {6:1--6:21},
year = {2022},
url = {https://doi.org/10.1145/3474597},
doi = {10.1145/3474597},
timestamp = {Fri, 11 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WuWCWH22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZengDSLLGZGWY22,
author = {Shulin Zeng and
Guohao Dai and
Hanbo Sun and
Jun Liu and
Shiyao Li and
Guangjun Ge and
Kai Zhong and
Kaiyuan Guo and
Yu Wang and
Huazhong Yang},
title = {A Unified {FPGA} Virtualization Framework for General-Purpose Deep
Neural Networks in the Cloud},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {3},
pages = {24:1--24:31},
year = {2022},
url = {https://doi.org/10.1145/3480170},
doi = {10.1145/3480170},
timestamp = {Wed, 07 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZengDSLLGZGWY22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangCK22,
author = {Niansong Zhang and
Xiang Chen and
Nachiket Kapre},
title = {RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic
Arrays Using Evolutionary Algorithm},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {4},
pages = {38:1--38:23},
year = {2022},
url = {https://doi.org/10.1145/3501803},
doi = {10.1145/3501803},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangCK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhouMLKS22,
author = {Yun Zhou and
Pongstorn Maidee and
Chris Lavin and
Alireza Kaviani and
Dirk Stroobandt},
title = {RWRoute: An Open-source Timing-driven Router for Commercial FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {15},
number = {1},
pages = {8:1--8:27},
year = {2022},
url = {https://doi.org/10.1145/3491236},
doi = {10.1145/3491236},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhouMLKS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Al-HyariSSMGA21,
author = {Abeer Y. Al{-}Hyari and
Hannah Szentimrey and
Ahmed Shamli and
Timothy Martin and
Gary Gr{\'{e}}wal and
Shawki Areibi},
title = {A Deep Learning Framework to Predict Routability for {FPGA} Circuit
Placement},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {3},
pages = {16:1--16:28},
year = {2021},
url = {https://doi.org/10.1145/3465373},
doi = {10.1145/3465373},
timestamp = {Fri, 17 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Al-HyariSSMGA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChoPFM21,
author = {Shenghsun Cho and
Mrunal Patel and
Michael Ferdman and
Peter A. Milder},
title = {Practical Model Checking on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {2},
pages = {8:1--8:18},
year = {2021},
url = {https://doi.org/10.1145/3448272},
doi = {10.1145/3448272},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChoPFM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuWXW21,
author = {Zhenghua Gu and
Wenqin Wan and
Jundong Xie and
Chang Wu},
title = {Dependency Graph-based High-level Synthesis for Maximum Instruction
Parallelism},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {4},
pages = {20:1--20:15},
year = {2021},
url = {https://doi.org/10.1145/3468875},
doi = {10.1145/3468875},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GuWXW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HungLWSGWS21,
author = {Jos{\'{e}} Romero Hung and
Chao Li and
Pengyu Wang and
Chuanming Shao and
Jinyang Guo and
Jing Wang and
Guoyong Shi},
title = {{ACE-GCN:} {A} Fast Data-driven {FPGA} Accelerator for {GCN} Embedding},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {4},
pages = {21:1--21:23},
year = {2021},
url = {https://doi.org/10.1145/3470536},
doi = {10.1145/3470536},
timestamp = {Wed, 24 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HungLWSGWS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LaiUXFRZ21,
author = {Yi{-}Hsiang Lai and
Ecenur Ustun and
Shaojie Xiang and
Zhenman Fang and
Hongbo Rong and
Zhiru Zhang},
title = {Programming and Synthesis for Software-defined {FPGA} Acceleration:
Status and Future Prospects},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {4},
pages = {17:1--17:39},
year = {2021},
url = {https://doi.org/10.1145/3469660},
doi = {10.1145/3469660},
timestamp = {Wed, 06 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LaiUXFRZ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MaHTNSPLSDC21,
author = {Rui Ma and
Jia{-}Ching Hsu and
Tian Tan and
Eriko Nurvitadhi and
David Sheffield and
Rob Pelt and
Martin Langhammer and
Jaewoong Sim and
Aravind Dasu and
Derek Chiou},
title = {Specializing {FGPU} for Persistent Deep Learning},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {2},
pages = {10:1--10:23},
year = {2021},
url = {https://doi.org/10.1145/3457886},
doi = {10.1145/3457886},
timestamp = {Thu, 29 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MaHTNSPLSDC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PeetermansRV21,
author = {Adriaan Peetermans and
Vladimir Rozic and
Ingrid Verbauwhede},
title = {Design and Analysis of Configurable Ring Oscillators for True Random
Number Generation Based on Coherent Sampling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {2},
pages = {7:1--7:20},
year = {2021},
url = {https://doi.org/10.1145/3433166},
doi = {10.1145/3433166},
timestamp = {Fri, 13 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PeetermansRV21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ReggianiSCNMS21,
author = {Enrico Reggiani and
Emanuele Del Sozzo and
Davide Conficconi and
Giuseppe Natale and
Carlo Moroni and
Marco D. Santambrogio},
title = {Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly
Optimized {HDL} Components},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {3},
pages = {15:1--15:33},
year = {2021},
url = {https://doi.org/10.1145/3461478},
doi = {10.1145/3461478},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ReggianiSCNMS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SabogalGC21,
author = {Sebastian Sabogal and
Alan D. George and
Gary Crum},
title = {Reconfigurable Framework for Resilient Semantic Segmentation for Space
Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {4},
pages = {22:1--22:32},
year = {2021},
url = {https://doi.org/10.1145/3472770},
doi = {10.1145/3472770},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SabogalGC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SasongkoKWRM21,
author = {Arif Sasongko and
I. M. Narendra Kumara and
Arief Wicaksana and
Fr{\'{e}}d{\'{e}}ric Rousseau and
Olivier Muller},
title = {Hardware Context Switch-based Cryptographic Accelerator for Handling
Multiple Streams},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {3},
pages = {14:1--14:25},
year = {2021},
url = {https://doi.org/10.1145/3460941},
doi = {10.1145/3460941},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SasongkoKWRM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TakaMLS21,
author = {Endri Taka and
Konstantinos Maragos and
George Lentaris and
Dimitrios Soudris},
title = {Process Variability Analysis in Interconnect, Logic, and Arithmetic
Blocks of 16-nm FinFET FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {3},
pages = {13:1--13:30},
year = {2021},
url = {https://doi.org/10.1145/3458843},
doi = {10.1145/3458843},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TakaMLS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WijtvlietCK21,
author = {Mark Wijtvliet and
Henk Corporaal and
Akash Kumar},
title = {{CGRA-EAM} - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable
Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {4},
pages = {19:1--19:28},
year = {2021},
url = {https://doi.org/10.1145/3468874},
doi = {10.1145/3468874},
timestamp = {Wed, 06 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WijtvlietCK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YangHKLHYLLJ21,
author = {Tao Yang and
Zhezhi He and
Tengchuan Kou and
Qingzheng Li and
Qi Han and
Haibao Yu and
Fangxin Liu and
Yun Liang and
Li Jiang},
title = {{BISWSRBS:} {A} Winograd-based {CNN} Accelerator with a Fine-grained
Regular Sparsity Pattern and Mixed Precision Quantization},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {4},
pages = {18:1--18:28},
year = {2021},
url = {https://doi.org/10.1145/3467476},
doi = {10.1145/3467476},
timestamp = {Thu, 07 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YangHKLHYLLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YasudoCVLABG21,
author = {Ryota Yasudo and
Jos{\'{e}} Gabriel de Figueiredo Coutinho and
Ana Lucia Varbanescu and
Wayne Luk and
Hideharu Amano and
Tobias Becker and
Ce Guo},
title = {Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow
Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {3},
pages = {12:1--12:21},
year = {2021},
url = {https://doi.org/10.1145/3452742},
doi = {10.1145/3452742},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YasudoCVLABG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhouHLLC21,
author = {Zhen Zhou and
Debiao He and
Zhe Liu and
Min Luo and
Kim{-}Kwang Raymond Choo},
title = {A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {2},
pages = {11:1--11:21},
year = {2021},
url = {https://doi.org/10.1145/3447812},
doi = {10.1145/3447812},
timestamp = {Mon, 20 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhouHLLC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AlachiotisVCP20,
author = {Nikolaos Alachiotis and
Charalampos Vatsolakis and
Grigorios Chrysos and
Dionisios N. Pnevmatikatos},
title = {RAiSD-X: {A} Fast and Accurate {FPGA} System for the Detection of
Positive Selection in Thousands of Genomes},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {1},
pages = {2:1--2:30},
year = {2020},
url = {https://doi.org/10.1145/3364225},
doi = {10.1145/3364225},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/AlachiotisVCP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AttiaB20,
author = {Sameh Attia and
Vaughn Betz},
title = {Feel Free to Interrupt: Safe Task Stopping to Enable {FPGA} Checkpointing
and Context Switching},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {1},
pages = {3:1--3:27},
year = {2020},
url = {https://doi.org/10.1145/3372491},
doi = {10.1145/3372491},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AttiaB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BeasleyCW20,
author = {Alexander E. Beasley and
Christopher T. Clarke and
Robert J. Watson},
title = {An OpenGL Compliant Hardware Implementation of a Graphic Processing
Unit Using Field Programmable Gate Array-System on Chip Technology},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {1},
pages = {2:1--2:24},
year = {2020},
url = {https://doi.org/10.1145/3410357},
doi = {10.1145/3410357},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/BeasleyCW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BestaFBSLH20,
author = {Maciej Besta and
Marc Fischer and
Tal Ben{-}Nun and
Dimitri Stanojevic and
Johannes de Fine Licht and
Torsten Hoefler},
title = {Substream-Centric Maximum Matchings on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {2},
pages = {8:1--8:33},
year = {2020},
url = {https://doi.org/10.1145/3377871},
doi = {10.1145/3377871},
timestamp = {Fri, 10 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BestaFBSLH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DeHon20,
author = {Andr{\'{e}} DeHon},
title = {Introduction to Special Section on {FCCM} 2019},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {4},
pages = {17:1--17:2},
year = {2020},
url = {https://doi.org/10.1145/3410373},
doi = {10.1145/3410373},
timestamp = {Sun, 11 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DeHon20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DelomierGCJ20,
author = {Yann Delomier and
Bertrand Le Gal and
J{\'{e}}r{\'{e}}mie Crenne and
Christophe J{\'{e}}go},
title = {Model-based Design of Hardware {SC} Polar Decoders for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {2},
pages = {10:1--10:27},
year = {2020},
url = {https://doi.org/10.1145/3391431},
doi = {10.1145/3391431},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DelomierGCJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/EldafrawyBYB20,
author = {Mohamed Eldafrawy and
Andrew Boutros and
Sadegh Yazdanshenas and
Vaughn Betz},
title = {{FPGA} Logic Block Architectures for Efficient Deep Learning Inference},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {3},
pages = {12:1--12:34},
year = {2020},
url = {https://doi.org/10.1145/3393668},
doi = {10.1145/3393668},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/EldafrawyBYB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FraserL20,
author = {Nicholas J. Fraser and
Philip H. W. Leong},
title = {Kernel Normalised Least Mean Squares with Delayed Model Adaptation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {2},
pages = {7:1--7:30},
year = {2020},
url = {https://doi.org/10.1145/3376924},
doi = {10.1145/3376924},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/FraserL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GargWPK20,
author = {Tushar Garg and
Saud Wasly and
Rodolfo Pellizzoni and
Nachiket Kapre},
title = {HopliteBuf: Network Calculus-Based Design of {FPGA} NoCs with Provably
Stall-Free FIFOs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {2},
pages = {6:1--6:35},
year = {2020},
url = {https://doi.org/10.1145/3375899},
doi = {10.1145/3375899},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GargWPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/IoannouGMPPPM20,
author = {Aggelos D. Ioannou and
Konstantinos Georgopoulos and
Pavlos Malakonakis and
Dionisios N. Pnevmatikatos and
Vassilis D. Papaefstathiou and
Ioannis Papaefstathiou and
Iakovos Mavroidis},
title = {{UNILOGIC:} {A} Novel Architecture for Highly Parallel Reconfigurable
Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {4},
pages = {21:1--21:32},
year = {2020},
url = {https://doi.org/10.1145/3409115},
doi = {10.1145/3409115},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/IoannouGMPPPM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JamalCGW20,
author = {Al{-}Shahna Jamal and
Eli Cahill and
Jeffrey Goeders and
Steven J. E. Wilton},
title = {Fast Turnaround {HLS} Debugging Using Dependency Analysis and Debug
Overlays},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {1},
pages = {4:1--4:26},
year = {2020},
url = {https://doi.org/10.1145/3372490},
doi = {10.1145/3372490},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JamalCGW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KaraA20,
author = {Kaan Kara and
Gustavo Alonso},
title = {PipeArch: Generic and Context-Switch Capable Data Processing on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {1},
pages = {3:1--3:28},
year = {2020},
url = {https://doi.org/10.1145/3418465},
doi = {10.1145/3418465},
timestamp = {Fri, 11 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KaraA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KourfaliS20,
author = {Alexandra Kourfali and
Dirk Stroobandt},
title = {In-Circuit Debugging with Dynamic Reconfiguration of {FPGA} Interconnects},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {1},
pages = {5:1--5:29},
year = {2020},
url = {https://doi.org/10.1145/3375459},
doi = {10.1145/3375459},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KourfaliS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KyparissasD20,
author = {Nikolaos Kyparissas and
Apostolos Dollas},
title = {Large-scale Cellular Automata on FPGAs: {A} New Generic Architecture
and a Framework},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {1},
pages = {5:1--5:32},
year = {2020},
url = {https://doi.org/10.1145/3423185},
doi = {10.1145/3423185},
timestamp = {Fri, 04 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KyparissasD20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LaMGPK20,
author = {Tuan Minh La and
Kaspar Matas and
Nikola Grunchevski and
Khoa Dang Pham and
Dirk Koch},
title = {FPGADefender: Malicious Self-oscillator Scanning for Xilinx UltraScale
+ FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {3},
pages = {15:1--15:31},
year = {2020},
url = {https://doi.org/10.1145/3402937},
doi = {10.1145/3402937},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LaMGPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Mohajer0BL20,
author = {Soheil Mohajer and
Zhiheng Wang and
Kia Bazargan and
Yuyang Li},
title = {Parallel Unary Computing Based on Function Derivatives},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {1},
pages = {4:1--4:25},
year = {2020},
url = {https://doi.org/10.1145/3418464},
doi = {10.1145/3418464},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/Mohajer0BL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MuZLS20,
author = {Jiandong Mu and
Wei Zhang and
Hao Liang and
Sharad Sinha},
title = {Optimizing OpenCL-Based {CNN} Design on {FPGA} with Comprehensive
Design Space Exploration and Collaborative Performance Modeling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {3},
pages = {13:1--13:28},
year = {2020},
url = {https://doi.org/10.1145/3397514},
doi = {10.1145/3397514},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MuZLS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MurrayPZWELSGWW20,
author = {Kevin E. Murray and
Oleg Petelin and
Sheng Zhong and
Jia Min Wang and
Mohamed Eldafrawy and
Jean{-}Philippe Legault and
Eugene Sha and
Aaron Graham and
Jean Wu and
Matthew J. P. Walker and
Hanqing Zeng and
Panagiotis Patros and
Jason Luu and
Kenneth B. Kent and
Vaughn Betz},
title = {{VTR} 8: High-performance {CAD} and Customizable {FPGA} Architecture
Modelling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {2},
pages = {9:1--9:55},
year = {2020},
url = {https://doi.org/10.1145/3388617},
doi = {10.1145/3388617},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MurrayPZWELSGWW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SabogalGW20,
author = {Sebastian Sabogal and
Alan D. George and
Christopher M. Wilson},
title = {Reconfigurable Framework for Environmentally Adaptive Resilience in
Hybrid Space Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {3},
pages = {14:1--14:32},
year = {2020},
url = {https://doi.org/10.1145/3398380},
doi = {10.1145/3398380},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SabogalGW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SerreP20,
author = {Fran{\c{c}}ois Serre and
Markus P{\"{u}}schel},
title = {DSL-Based Hardware Generation with Scala: Example Fast Fourier Transforms
and Sorting Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {1},
pages = {1:1--1:23},
year = {2020},
url = {https://doi.org/10.1145/3359754},
doi = {10.1145/3359754},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SerreP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShaoLLLJ20,
author = {Zhiyuan Shao and
Chenhao Liu and
Ruoshi Li and
Xiaofei Liao and
Hai Jin},
title = {Processing Grid-format Real-world Graphs on DRAM-based {FPGA} Accelerators
with Application-specific Caching Mechanisms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {3},
pages = {11:1--11:33},
year = {2020},
url = {https://doi.org/10.1145/3391920},
doi = {10.1145/3391920},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ShaoLLLJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TangWGZW20,
author = {Qi Tang and
Zhe Wang and
Biao Guo and
Li{-}Hua Zhu and
Ji{-}Bo Wei},
title = {Partitioning and Scheduling with Module Merging on Dynamic Partial
Reconfigurable FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {3},
pages = {16:1--16:24},
year = {2020},
url = {https://doi.org/10.1145/3403702},
doi = {10.1145/3403702},
timestamp = {Sat, 18 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/TangWGZW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/VaishnavPPK20,
author = {Anuj Vaishnav and
Khoa Dang Pham and
Joseph Powell and
Dirk Koch},
title = {{FOS:} {A} Modular {FPGA} Operating System for Dynamic Workloads},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {4},
pages = {20:1--20:28},
year = {2020},
url = {https://doi.org/10.1145/3405794},
doi = {10.1145/3405794},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/VaishnavPPK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangSPD0T20,
author = {Xuzhi Zhang and
Xiaozhe Shao and
George Provelengios and
Naveen Kumar Dumpala and
Lixin Gao and
Russell Tessier},
title = {CoNFV: {A} Heterogeneous Platform for Scalable Network Function Virtualization},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {14},
number = {1},
pages = {1:1--1:29},
year = {2020},
url = {https://doi.org/10.1145/3409113},
doi = {10.1145/3409113},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangSPD0T20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangZBLL20,
author = {Jialiang Zhang and
Yue Zha and
Nicholas Beckwith and
Bangya Liu and
Jing Li},
title = {{MEG:} {A} RISCV-based System Emulation Infrastructure for Near-data
Processing Using FPGAs and High-bandwidth Memory},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {4},
pages = {19:1--19:24},
year = {2020},
url = {https://doi.org/10.1145/3409114},
doi = {10.1145/3409114},
timestamp = {Sun, 11 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangZBLL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhouVS20,
author = {Yun Zhou and
Dries Vercruyce and
Dirk Stroobandt},
title = {Accelerating {FPGA} Routing Through Algorithmic Enhancements and Connection-aware
Parallelization},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {13},
number = {4},
pages = {18:1--18:26},
year = {2020},
url = {https://doi.org/10.1145/3406959},
doi = {10.1145/3406959},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ZhouVS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AhmedZMTB19,
author = {Ibrahim Ahmed and
Shuze Zhao and
James Meijers and
Olivier Trescases and
Vaughn Betz},
title = {FRoC 2.0: Automatic {BRAM} and Logic Testing to Enable Dynamic Voltage
Scaling for {FPGA} Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {4},
pages = {20:1--20:28},
year = {2019},
url = {https://doi.org/10.1145/3354188},
doi = {10.1145/3354188},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/AhmedZMTB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Al-HyariAMGAV19,
author = {Abeer Y. Al{-}Hyari and
Ziad Abuowaimer and
Timothy Martin and
Gary Gr{\'{e}}wal and
Shawki Areibi and
Anthony Vannelli},
title = {Novel Congestion-estimation and Routability-prediction Methods based
on Machine Learning for Modern FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {3},
pages = {16:1--16:25},
year = {2019},
url = {https://doi.org/10.1145/3337930},
doi = {10.1145/3337930},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/Al-HyariAMGAV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BoDXWSS19,
author = {Chunkun Bo and
Vinh Dang and
Ted Xie and
Jack Wadden and
Mircea Stan and
Kevin Skadron},
title = {Automata Processing in Reconfigurable Architectures: In-the-Cloud
Deployment, Cross-Platform Evaluation, and Fast Symbol-Only Reconfiguration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {2},
pages = {9:1--9:25},
year = {2019},
url = {https://doi.org/10.1145/3314576},
doi = {10.1145/3314576},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BoDXWSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BobdaTEK19,
author = {Christophe Bobda and
Russell Tessier and
Ken Eguro and
Ryan Kastner},
title = {Introduction to the Special Section on Security in FPGA-accelerated
Cloud and Datacenters},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {3},
year = {2019},
url = {https://doi.org/10.1145/3352060},
doi = {10.1145/3352060},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BobdaTEK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CaoNZWXDWZC18,
author = {Shijie Cao and
Lanshun Nie and
De{-}chen Zhan and
Wenqiang Wang and
Ningyi Xu and
Ramashis Das and
Ming Wu and
Lintao Zhang and
Derek Chiou},
title = {FlexSaaS: {A} Reconfigurable Accelerator for Web Search Selection},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {1},
pages = {5:1--5:20},
year = {2019},
url = {https://doi.org/10.1145/3301409},
doi = {10.1145/3301409},
timestamp = {Sat, 15 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CaoNZWXDWZC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Chen19,
author = {Deming Chen},
title = {Editorial: {A} Message from the New Editor-in-Chief},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {2},
year = {2019},
url = {https://doi.org/10.1145/3326451},
doi = {10.1145/3326451},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Chen19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChoiCFHRW18,
author = {Young{-}kyu Choi and
Jason Cong and
Zhenman Fang and
Yuchen Hao and
Glenn Reinman and
Peng Wei},
title = {In-Depth Analysis on Microarchitectures of Modern Heterogeneous {CPU-FPGA}
Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {1},
pages = {4:1--4:20},
year = {2019},
url = {https://doi.org/10.1145/3294054},
doi = {10.1145/3294054},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChoiCFHRW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DumpalaPHT19,
author = {Naveen Kumar Dumpala and
Shivukumar B. Patil and
Daniel E. Holcomb and
Russell Tessier},
title = {Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable
Gate Arrays},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {26:1--26:23},
year = {2019},
url = {https://doi.org/10.1145/3289186},
doi = {10.1145/3289186},
timestamp = {Fri, 07 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DumpalaPHT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ElrabaaAA19,
author = {Muhammad E. S. Elrabaa and
Mohamed A. Al{-}Asli and
Marwan H. Abu{-}Amara},
title = {A Protection and Pay-per-use Licensing Scheme for On-cloud {FPGA}
Circuit IPs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {3},
pages = {13:1--13:19},
year = {2019},
url = {https://doi.org/10.1145/3329861},
doi = {10.1145/3329861},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ElrabaaAA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/EngelhardtS19,
author = {Nina Engelhardt and
Hayden Kwok{-}Hay So},
title = {GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {4},
pages = {21:1--21:28},
year = {2019},
url = {https://doi.org/10.1145/3357596},
doi = {10.1145/3357596},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/EngelhardtS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GiechaskielER19,
author = {Ilias Giechaskiel and
Ken Eguro and
Kasper Bonne Rasmussen},
title = {Leakier Wires: Exploiting {FPGA} Long Wires for Covert- and Side-channel
Attacks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {3},
pages = {11:1--11:29},
year = {2019},
url = {https://doi.org/10.1145/3322483},
doi = {10.1145/3322483},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GiechaskielER19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GorskiH19,
author = {Jason Gorski and
Darrin M. Hanna},
title = {The FPOA, a Medium-grained Reconfigurable Architecture for High-level
Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {4},
pages = {18:1--18:31},
year = {2019},
url = {https://doi.org/10.1145/3340556},
doi = {10.1145/3340556},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GorskiH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuoZYWY18,
author = {Kaiyuan Guo and
Shulin Zeng and
Jincheng Yu and
Yu Wang and
Huazhong Yang},
title = {{[DL]} {A} Survey of FPGA-based Neural Network Inference Accelerators},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {1},
pages = {2:1--2:26},
year = {2019},
url = {https://doi.org/10.1145/3289185},
doi = {10.1145/3289185},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GuoZYWY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KrautterGT19,
author = {Jonas Krautter and
Dennis R. E. Gnad and
Mehdi Baradaran Tahoori},
title = {Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs
in the Cloud},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {3},
pages = {12:1--12:26},
year = {2019},
url = {https://doi.org/10.1145/3328222},
doi = {10.1145/3328222},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KrautterGT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KrohD19,
author = {Alexander Kroh and
Oliver Diessel},
title = {Efficient Fine-grained Processor-logic Interactions on the Cache-coherent
Zynq Platform},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {25:1--25:22},
year = {2019},
url = {https://doi.org/10.1145/3277506},
doi = {10.1145/3277506},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KrohD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LattuadaF19,
author = {Marco Lattuada and
Fabrizio Ferrandi},
title = {A Design Flow Engine for the Support of Customized Dynamic High Level
Synthesis Flows},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {4},
pages = {19:1--19:26},
year = {2019},
url = {https://doi.org/10.1145/3356475},
doi = {10.1145/3356475},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LattuadaF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiYZZZ18,
author = {Wensong Li and
Fan Yang and
Hengliang Zhu and
Xuan Zeng and
Dian Zhou},
title = {An Efficient Memory Partitioning Approach for Multi-Pattern Data Access
via Data Reuse},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {1},
pages = {1:1--1:22},
year = {2019},
url = {https://doi.org/10.1145/3301296},
doi = {10.1145/3301296},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiYZZZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuZ19,
author = {Gai Liu and
Zhiru Zhang},
title = {PIMap: {A} Flexible Framework for Improving LUT-Based Technology Mapping
via Parallelized Iterative Optimization},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {23:1--23:23},
year = {2019},
url = {https://doi.org/10.1145/3268344},
doi = {10.1145/3268344},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuanNL19,
author = {Dinh Van Luan and
Xuan Truong Nguyen and
Hyuk{-}Jae Lee},
title = {A Novel {FPGA} Implementation of a Time-to-Digital Converter Supporting
Run-Time Estimation and Compensation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {2},
pages = {10:1--10:21},
year = {2019},
url = {https://doi.org/10.1145/3322482},
doi = {10.1145/3322482},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LuanNL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MorcelHSAAKK19,
author = {Raghid Morcel and
Hazem M. Hajj and
Mazen A. R. Saghir and
Haitham Akkary and
Hassan Artail and
Rahul Khanna and
Anil S. Keshavamurthy},
title = {FeatherNet: An Accelerated Convolutional Neural Network Design for
Resource-constrained FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {2},
pages = {6:1--6:27},
year = {2019},
url = {https://doi.org/10.1145/3306202},
doi = {10.1145/3306202},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MorcelHSAAKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/OppermannRSKS19,
author = {Julian Oppermann and
Melanie Reuter{-}Oppermann and
Lukas Sommer and
Andreas Koch and
Oliver Sinnen},
title = {Exact and Practical Modulo Scheduling for High-Level Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {2},
pages = {8:1--8:26},
year = {2019},
url = {https://doi.org/10.1145/3317670},
doi = {10.1145/3317670},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/OppermannRSKS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/OwaidaKA19,
author = {Muhsen Owaida and
Amit Kulkarni and
Gustavo Alonso},
title = {Distributed Inference over Decision Tree Ensembles on Clusters of
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {4},
pages = {17:1--17:27},
year = {2019},
url = {https://doi.org/10.1145/3340263},
doi = {10.1145/3340263},
timestamp = {Mon, 10 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/OwaidaKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TridgellKHBMZL19,
author = {Stephen Tridgell and
Martin Kumm and
Martin Hardieck and
David Boland and
Duncan J. M. Moss and
Peter Zipf and
Philip H. W. Leong},
title = {Unrolling Ternary Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {4},
pages = {22:1--22:23},
year = {2019},
url = {https://doi.org/10.1145/3359983},
doi = {10.1145/3359983},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TridgellKHBMZL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/UmurogluCRPS19,
author = {Yaman Umuroglu and
Davide Conficconi and
Lahiru Rasnayake and
Thomas B. Preu{\ss}er and
Magnus Sj{\"{a}}lander},
title = {Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {3},
pages = {15:1--15:24},
year = {2019},
url = {https://doi.org/10.1145/3337929},
doi = {10.1145/3337929},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/UmurogluCRPS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WangTS19,
author = {Haomiao Wang and
Prabu Thiagaraj and
Oliver Sinnen},
title = {FPGA-based Acceleration of {FT} Convolution for Pulsar Search Using
OpenCL},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {24:1--24:25},
year = {2019},
url = {https://doi.org/10.1145/3268933},
doi = {10.1145/3268933},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WangTS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YazdanshenasB18,
author = {Sadegh Yazdanshenas and
Vaughn Betz},
title = {{COFFE} 2: Automatic Modelling and Optimization of Complex and Heterogeneous
{FPGA} Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {1},
pages = {3:1--3:27},
year = {2019},
url = {https://doi.org/10.1145/3301298},
doi = {10.1145/3301298},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/YazdanshenasB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangQ19,
author = {Jiliang Zhang and
Gang Qu},
title = {Recent Attacks and Defenses on FPGA-based Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {3},
pages = {14:1--14:24},
year = {2019},
url = {https://doi.org/10.1145/3340557},
doi = {10.1145/3340557},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ZhangQ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhouWM19,
author = {Xuegong Zhou and
Lingli Wang and
Alan Mishchenko},
title = {Fast Adjustable {NPN} Classification Using Generalized Symmetries},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {12},
number = {2},
pages = {7:1--7:16},
year = {2019},
url = {https://doi.org/10.1145/3313917},
doi = {10.1145/3313917},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ZhouWM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AnandakumarDSH18,
author = {N. Nalla Anandakumar and
M. Prem Laxman Das and
Somitra Kumar Sanadhya and
Mohammad S. Hashmi},
title = {Reconfigurable Hardware Architecture for Authenticated Key Agreement
Protocol Over Binary Edwards Curve},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {12:1--12:19},
year = {2018},
url = {https://doi.org/10.1145/3231743},
doi = {10.1145/3231743},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AnandakumarDSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Bakos18,
author = {Jason D. Bakos},
title = {Introduction to the Special Section on FCCM'16},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
year = {2018},
url = {https://doi.org/10.1145/3183572},
doi = {10.1145/3183572},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Bakos18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BlottPFGOULV18,
author = {Michaela Blott and
Thomas B. Preu{\ss}er and
Nicholas J. Fraser and
Giulio Gambardella and
Kenneth O'Brien and
Yaman Umuroglu and
Miriam Leeser and
Kees A. Vissers},
title = {FINN-\emph{R}: An End-to-End Deep-Learning Framework for Fast Exploration
of Quantized Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {16:1--16:23},
year = {2018},
url = {https://doi.org/10.1145/3242897},
doi = {10.1145/3242897},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/BlottPFGOULV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BoutrosYB18,
author = {Andrew Boutros and
Sadegh Yazdanshenas and
Vaughn Betz},
title = {You Cannot Improve What You Do not Measure: {FPGA} vs. {ASIC} Efficiency
Gaps for Convolutional Neural Network Inference},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {20:1--20:23},
year = {2018},
url = {https://doi.org/10.1145/3242898},
doi = {10.1145/3242898},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/BoutrosYB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenPW18,
author = {Deming Chen and
Andrew Putnam and
Steven J. E. Wilton},
title = {Introduction to the Special Section on Deep Learning in FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {14:1--14:3},
year = {2018},
url = {https://doi.org/10.1145/3294768},
doi = {10.1145/3294768},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChenPW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DaigneaultD18,
author = {Marc{-}Andr{\'{e}} Daigneault and
Jean{-}Pierre David},
title = {Automated Synthesis of Streaming Transfer Level Hardware Designs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {13:1--13:22},
year = {2018},
url = {https://doi.org/10.1145/3243930},
doi = {10.1145/3243930},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DaigneaultD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DavisHLSCC18,
author = {James J. Davis and
Eddie Hung and
Joshua M. Levine and
Edward A. Stott and
Peter Y. K. Cheung and
George A. Constantinides},
title = {KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation
for {FPGA} Designs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {2:1--2:22},
year = {2018},
url = {https://doi.org/10.1145/3129789},
doi = {10.1145/3129789},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DavisHLSCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DingLBM18,
author = {Ruizhou Ding and
Zeye Liu and
R. D. (Shawn) Blanton and
Diana Marculescu},
title = {Lightening the Load with Highly Accurate Storage- and Energy-Efficient
LightNNs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {17:1--17:24},
year = {2018},
url = {https://doi.org/10.1145/3270689},
doi = {10.1145/3270689},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DingLBM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GiesenGRKD18,
author = {Hans Giesen and
Benjamin Gojman and
Raphael Rubin and
Ji Kim and
Andr{\'{e}} DeHon},
title = {Continuous Online Self-Monitoring Introspection Circuitry for Timing
Repair by Incremental Partial-Reconfiguration {(COSMIC} {TRIP)}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {3:1--3:23},
year = {2018},
url = {https://doi.org/10.1145/3158229},
doi = {10.1145/3158229},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GiesenGRKD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KadiJMH18,
author = {Muhammed Al Kadi and
Benedikt Jan{\ss}en and
Jones Yudi Mori and
Michael H{\"{u}}bner},
title = {General-Purpose Computing with Soft GPUs on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {5:1--5:22},
year = {2018},
url = {https://doi.org/10.1145/3173548},
doi = {10.1145/3173548},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KadiJMH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KhanY18,
author = {Farheen Fatima Khan and
Andy Gean Ye},
title = {An Evaluation on the Accuracy of the Minimum-Width Transistor Area
Models in Ranking the Layout Area of {FPGA} Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {8:1--8:23},
year = {2018},
url = {https://doi.org/10.1145/3182394},
doi = {10.1145/3182394},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KhanY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuFNNCL18,
author = {Shuanglong Liu and
Hongxiang Fan and
Xinyu Niu and
Ho{-}Cheung Ng and
Yang Chu and
Wayne Luk},
title = {Optimizing CNN-based Segmentation with Deeply Customized Convolutional
and Deconvolutional Architectures on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {19:1--19:22},
year = {2018},
url = {https://doi.org/10.1145/3242900},
doi = {10.1145/3242900},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuFNNCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MeloniCDBCRRB18,
author = {Paolo Meloni and
Alessandro Capotondi and
Gianfranco Deriu and
Michele Brian and
Francesco Conti and
Davide Rossi and
Luigi Raffo and
Luca Benini},
title = {NEURAghe: Exploiting {CPU-FPGA} Synergies for Efficient and Flexible
{CNN} Inference Acceleration on Zynq SoCs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {18:1--18:24},
year = {2018},
url = {https://doi.org/10.1145/3284357},
doi = {10.1145/3284357},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MeloniCDBCRRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PetelinB18,
author = {Oleg Petelin and
Vaughn Betz},
title = {Wotan: Evaluating {FPGA} Architecture Routability without Benchmarks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {11:1--11:23},
year = {2018},
url = {https://doi.org/10.1145/3195800},
doi = {10.1145/3195800},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PetelinB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Prost-BoucleBP18,
author = {Adrien Prost{-}Boucle and
Alban Bourge and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {High-Efficiency Convolutional Ternary Neural Networks with Custom
Adder Trees and Weight Compression},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {15:1--15:24},
year = {2018},
url = {https://doi.org/10.1145/3270764},
doi = {10.1145/3270764},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Prost-BoucleBP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RossiDBBH18,
author = {Enrico Rossi and
Marvin Damschen and
Lars Bauer and
Giorgio C. Buttazzo and
J{\"{o}}rg Henkel},
title = {Preemption of the Partial Reconfiguration Process to Enable Real-Time
Computing With FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {10:1--10:24},
year = {2018},
url = {https://doi.org/10.1145/3182183},
doi = {10.1145/3182183},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RossiDBBH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RouhaniHLK18,
author = {Bita Darvish Rouhani and
Siam Umar Hussain and
Kristin E. Lauter and
Farinaz Koushanfar},
title = {ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in
Clouds Using FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {21:1--21:21},
year = {2018},
url = {https://doi.org/10.1145/3242899},
doi = {10.1145/3242899},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/RouhaniHLK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/StewartDMGBW18,
author = {Rob Stewart and
Kirsty Duncan and
Greg Michaelson and
Paulo Garcia and
Deepayan Bhowmik and
Andrew M. Wallace},
title = {{RIPL:} {A} Parallel Image Processing Language for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {7:1--7:24},
year = {2018},
url = {https://doi.org/10.1145/3180481},
doi = {10.1145/3180481},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/StewartDMGBW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TatsumuraYB18,
author = {Kosuke Tatsumura and
Sadegh Yazdanshenas and
Vaughn Betz},
title = {Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {6:1--6:22},
year = {2018},
url = {https://doi.org/10.1145/3154425},
doi = {10.1145/3154425},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TatsumuraYB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WijesunderaPSI18,
author = {Deshya Wijesundera and
Alok Prakash and
Thambipillai Srikanthan and
Achintha Ihalage},
title = {Framework for Rapid Performance Estimation of Embedded Soft Core Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {9:1--9:21},
year = {2018},
url = {https://doi.org/10.1145/3195801},
doi = {10.1145/3195801},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WijesunderaPSI18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WongBR18,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order
Soft Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {1:1--1:22},
year = {2018},
url = {https://doi.org/10.1145/3093741},
doi = {10.1145/3093741},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WongBR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YuGHNQGWY18,
author = {Jincheng Yu and
Guangjun Ge and
Yiming Hu and
Xuefei Ning and
Jiantao Qiu and
Kaiyuan Guo and
Yu Wang and
Huazhong Yang},
title = {Instruction Driven Cross-layer {CNN} Accelerator for Fast Detection
on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {22:1--22:23},
year = {2018},
url = {https://doi.org/10.1145/3283452},
doi = {10.1145/3283452},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/YuGHNQGWY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhaoNALCD18,
author = {Zhuoran Zhao and
Nguyen T. H. Nguyen and
Dimitris Agiakatsikas and
Ganghee Lee and
Ediz Cetin and
Oliver Diessel},
title = {Fine-Grained Module-Based Error Recovery in FPGA-Based {TMR} Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {4:1--4:23},
year = {2018},
url = {https://doi.org/10.1145/3173549},
doi = {10.1145/3173549},
timestamp = {Thu, 07 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ZhaoNALCD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BurovskiyGSL17,
author = {Pavel Burovskiy and
Paul Grigoras and
Spencer J. Sherwin and
Wayne Luk},
title = {Efficient Assembly for High-Order Unstructured {FEM} Meshes {(FPL}
2015)},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {12:1--12:22},
year = {2017},
url = {https://doi.org/10.1145/3024064},
doi = {10.1145/3024064},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/BurovskiyGSL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CardosoS17,
author = {Jo{\~{a}}o M. P. Cardoso and
Cristina Silvano},
title = {Introduction to the Special Section on {FPL} 2015},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {10:1--10:2},
year = {2017},
url = {https://doi.org/10.1145/3041224},
doi = {10.1145/3041224},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CardosoS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChuSK17,
author = {Thiem Van Chu and
Shimpei Sato and
Kenji Kise},
title = {Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip
Using a Single {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {4},
pages = {27:1--27:27},
year = {2017},
url = {https://doi.org/10.1145/3151758},
doi = {10.1145/3151758},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChuSK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FabryT17,
author = {Pieter Fabry and
David Thomas},
title = {Efficient Reconfigurable Architecture for Pricing Exotic Options},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {4},
pages = {29:1--29:22},
year = {2017},
url = {https://doi.org/10.1145/3158228},
doi = {10.1145/3158228},
timestamp = {Fri, 30 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/FabryT17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FraserLMFTJL17,
author = {Nicholas J. Fraser and
JunKyu Lee and
Duncan J. M. Moss and
Julian Faraone and
Stephen Tridgell and
Craig T. Jin and
Philip Heng Wai Leong},
title = {{FPGA} Implementations of Kernel Normalised Least Mean Squares Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {4},
pages = {26:1--26:20},
year = {2017},
url = {https://doi.org/10.1145/3106744},
doi = {10.1145/3106744},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/FraserLMFTJL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GerleinMBC17,
author = {Eduardo A. Gerlein and
Thomas Martin McGinnity and
Ammar Belatreche and
Sonya A. Coleman},
title = {Network on Chip Architecture for Multi-Agent Systems in {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {4},
pages = {25:1--25:22},
year = {2017},
url = {https://doi.org/10.1145/3121112},
doi = {10.1145/3121112},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GerleinMBC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuHO17,
author = {Chongyan Gu and
Neil Hanley and
M{\'{a}}ire O'Neill},
title = {Improved Reliability of FPGA-Based {PUF} Identification Generator
Design},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {20:1--20:23},
year = {2017},
url = {https://doi.org/10.1145/3053681},
doi = {10.1145/3053681},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GuHO17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KapreG17,
author = {Nachiket Kapre and
Jan Gray},
title = {Hoplite: {A} Deflection-Routed Directional Torus NoC for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {14:1--14:24},
year = {2017},
url = {https://doi.org/10.1145/3027486},
doi = {10.1145/3027486},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KapreG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KimA17,
author = {Jin Hee Kim and
Jason Helge Anderson},
title = {Synthesizable Standard Cell {FPGA} Fabrics Targetable by the Verilog-to-Routing
{CAD} Flow},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {11:1--11:23},
year = {2017},
url = {https://doi.org/10.1145/3024063},
doi = {10.1145/3024063},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KimA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LaForestA17,
author = {Charles Eric LaForest and
Jason Helge Anderson},
title = {Microarchitectural Comparison of the {MXP} and Octavo Soft-Processor
{FPGA} Overlays},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {19:1--19:25},
year = {2017},
url = {https://doi.org/10.1145/3053679},
doi = {10.1145/3053679},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LaForestA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LeongAABCDGHLLL17,
author = {Philip Heng Wai Leong and
Hideharu Amano and
Jason Helge Anderson and
Koen Bertels and
Jo{\~{a}}o M. P. Cardoso and
Oliver Diessel and
Guy Gogniat and
Mike Hutton and
JunKyu Lee and
Wayne Luk and
Patrick Lysaght and
Marco Platzner and
Viktor K. Prasanna and
Tero Rissa and
Cristina Silvano and
Hayden Kwok{-}Hay So and
Yu Wang},
title = {The First 25 Years of the {FPL} Conference: Significant Papers},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {15:1--15:17},
year = {2017},
url = {https://doi.org/10.1145/2996468},
doi = {10.1145/2996468},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LeongAABCDGHLLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuDJXLZX17,
author = {Zhiqiang Liu and
Yong Dou and
Jingfei Jiang and
Jinwei Xu and
Shijie Li and
Yongmei Zhou and
Yingnan Xu},
title = {Throughput-Optimized {FPGA} Accelerator for Deep Convolutional Neural
Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {17:1--17:23},
year = {2017},
url = {https://doi.org/10.1145/3079758},
doi = {10.1145/3079758},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LiuDJXLZX17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Prost-BouclePLA17,
author = {Adrien Prost{-}Boucle and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot and
Vincent Leroy and
Hande Alemdar},
title = {Efficient and Versatile {FPGA} Acceleration of Support Counting for
Stream Mining of Sequences and Frequent Itemsets},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {21:1--21:25},
year = {2017},
url = {https://doi.org/10.1145/3027485},
doi = {10.1145/3027485},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Prost-BouclePLA17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RieblerLMLP17,
author = {Heinrich Riebler and
Michael Lass and
Robert Mittendorf and
Thomas L{\"{o}}cke and
Christian Plessl},
title = {Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific
Designs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {24:1--24:23},
year = {2017},
url = {https://doi.org/10.1145/3053687},
doi = {10.1145/3053687},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/RieblerLMLP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Takano17,
author = {Shigeyuki Takano},
title = {Performance Scalability of Adaptive Processor Architecture},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {16:1--16:22},
year = {2017},
url = {https://doi.org/10.1145/3007902},
doi = {10.1145/3007902},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Takano17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TiliOS17,
author = {Ilian Tili and
Kalin Ovtcharov and
J. Gregory Steffan},
title = {Reducing the Performance Gap between Soft Scalar CPUs and Custom Hardware
with {TILT}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {22:1--22:23},
year = {2017},
url = {https://doi.org/10.1145/3079757},
doi = {10.1145/3079757},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TiliOS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/UenoSY17,
author = {Tomohiro Ueno and
Kentaro Sano and
Satoru Yamamoto},
title = {Bandwidth Compression of Floating-Point Numerical Data Streams for
FPGA-Based High-Performance Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {18:1--18:22},
year = {2017},
url = {https://doi.org/10.1145/3053688},
doi = {10.1145/3053688},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/UenoSY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WulfGG17,
author = {Nicholas Wulf and
Alan D. George and
Ann Gordon{-}Ross},
title = {Optimizing {FPGA} Performance, Power, and Dependability with Linear
Programming},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {3},
pages = {23:1--23:23},
year = {2017},
url = {https://doi.org/10.1145/3079756},
doi = {10.1145/3079756},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WulfGG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YangFWAE17,
author = {Hsin{-}Jung Yang and
Kermin Fleming and
Felix Winterstein and
Michael Adler and
Joel S. Emer},
title = {{(FPL} 2015) Scavenger: Automating the Construction of Application-Optimized
Memory Hierarchies},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {2},
pages = {13:1--13:23},
year = {2017},
url = {https://doi.org/10.1145/3009971},
doi = {10.1145/3009971},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/YangFWAE17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YoshimiOY17,
author = {Masato Yoshimi and
Yasin Oge and
Tsutomu Yoshinaga},
title = {Pipelined Parallel Join and Its FPGA-Based Acceleration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {4},
pages = {28:1--28:28},
year = {2017},
url = {https://doi.org/10.1145/3079759},
doi = {10.1145/3079759},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YoshimiOY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AbdelhadiL16,
author = {Ameer M. S. Abdelhadi and
Guy G. F. Lemieux},
title = {Modular Switched Multiported SRAM-Based Memories},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {3},
pages = {22:1--22:26},
year = {2016},
url = {https://doi.org/10.1145/2851506},
doi = {10.1145/2851506},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AbdelhadiL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AttiaTJZ16,
author = {Osama G. Attia and
Kevin R. Townsend and
Phillip H. Jones and
Joseph Zambreno},
title = {A Reconfigurable Architecture for the Detection of Strongly Connected
Components},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {16:1--16:19},
year = {2016},
url = {https://doi.org/10.1145/2807700},
doi = {10.1145/2807700},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AttiaTJZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BourgeMR16,
author = {Alban Bourge and
Olivier Muller and
Fr{\'{e}}d{\'{e}}ric Rousseau},
title = {Generating Efficient Context-Switch Capable Circuits through Autonomous
Design Flow},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {9:1--9:23},
year = {2016},
url = {https://doi.org/10.1145/2996199},
doi = {10.1145/2996199},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BourgeMR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChaoTH16,
author = {Hung{-}Lin Chao and
Sheng{-}Ya Tung and
Pao{-}Ann Hsiung},
title = {Dynamic Task Mapping with Congestion Speculation for Reconfigurable
Network-on-Chip},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {3:1--3:25},
year = {2016},
url = {https://doi.org/10.1145/2892633},
doi = {10.1145/2892633},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ChaoTH16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Chen16,
author = {Deming Chen},
title = {Introduction},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {28:1--28:2},
year = {2016},
url = {https://doi.org/10.1145/2955103},
doi = {10.1145/2955103},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Chen16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DeHonC16,
author = {Andr{\'{e}} DeHon and
Derek Chiou},
title = {Introduction to Special Issue on Reconfigurable Components with Source
Code},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {3},
pages = {19:1--19:2},
year = {2016},
url = {https://doi.org/10.1145/2907949},
doi = {10.1145/2907949},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DeHonC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FangL16,
author = {Xin Fang and
Miriam Leeser},
title = {Open-Source Variable-Precision Floating-Point Library for Major Commercial
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {3},
pages = {20:1--20:17},
year = {2016},
url = {https://doi.org/10.1145/2851507},
doi = {10.1145/2851507},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/FangL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GalBRS16,
author = {Bertrand Le Gal and
Y{\'{e}}rom{-}David Bromberg and
Laurent R{\'{e}}veill{\`{e}}re and
Jigar Solanki},
title = {A Flexible SoC and Its Methodology for Parser-Based Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {4:1--4:23},
year = {2016},
url = {https://doi.org/10.1145/2939379},
doi = {10.1145/2939379},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GalBRS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KadricLD16,
author = {Edin Kadric and
David Lakata and
Andr{\'{e}} DeHon},
title = {Impact of Parallelism and Memory Architecture on {FPGA} Communication
Energy},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {30:1--30:23},
year = {2016},
url = {https://doi.org/10.1145/2857057},
doi = {10.1145/2857057},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KadricLD16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Kapre16,
author = {Nachiket Kapre},
title = {Optimizing Soft Vector Processing in FPGA-Based Embedded Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {3},
pages = {17:1--17:17},
year = {2016},
url = {https://doi.org/10.1145/2912884},
doi = {10.1145/2912884},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Kapre16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KashyapC16,
author = {Hirak J. Kashyap and
Ricardo Chaves},
title = {Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {11:1--11:22},
year = {2016},
url = {https://doi.org/10.1145/2816822},
doi = {10.1145/2816822},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KashyapC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MatthewsSF16,
author = {Eric Matthews and
Lesley Shannon and
Alexandra Fedorova},
title = {Shared Memory Multicore MicroBlaze System with {SMP} Linux Support},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {26:1--26:22},
year = {2016},
url = {https://doi.org/10.1145/2870638},
doi = {10.1145/2870638},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MatthewsSF16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PangWPPFL16,
author = {Yeyong Pang and
Shaojun Wang and
Yu Peng and
Xiyuan Peng and
Nicholas J. Fraser and
Philip Heng Wai Leong},
title = {A Microcoded Kernel Recursive Least Squares Processor Using {FPGA}
Technology},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {5:1--5:22},
year = {2016},
url = {https://doi.org/10.1145/2950061},
doi = {10.1145/2950061},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/PangWPPFL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RaitzaVHP16,
author = {Michael Raitza and
Markus Vogt and
Christian Hochberger and
Thilo Pionteck},
title = {{RAW} 2014: Random Number Generators on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {15:1--15:21},
year = {2016},
url = {https://doi.org/10.1145/2807699},
doi = {10.1145/2807699},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RaitzaVHP16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RichardsonGCL16,
author = {Justin Richardson and
Alan D. George and
Kevin Cheng and
Herman Lam},
title = {Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational,
Memory, I/O, {\&} Realizable-Utilization Metrics},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {2:1--2:21},
year = {2016},
url = {https://doi.org/10.1145/2888401},
doi = {10.1145/2888401},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RichardsonGCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RodionovBR16,
author = {Alex Rodionov and
David Biancolin and
Jonathan Rose},
title = {Fine-Grained Interconnect Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {31:1--31:22},
year = {2016},
url = {https://doi.org/10.1145/2892641},
doi = {10.1145/2892641},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RodionovBR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RouhaniMSK16,
author = {Bita Darvish Rouhani and
Azalia Mirhoseini and
Ebrahim M. Songhori and
Farinaz Koushanfar},
title = {Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable
Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {8:1--8:22},
year = {2016},
url = {https://doi.org/10.1145/2974023},
doi = {10.1145/2974023},
timestamp = {Fri, 04 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RouhaniMSK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SantambrogioV16,
author = {Marco D. Santambrogio and
Ramachandran Vaidyanathan},
title = {Guest Editorial {RAW} 2014},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {13:1--13:2},
year = {2016},
url = {https://doi.org/10.1145/2841314},
doi = {10.1145/2841314},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SantambrogioV16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/StittSC16,
author = {Greg Stitt and
Eric Schwartz and
Patrick Cooke},
title = {A Parallel Sliding-Window Generator for High-Performance Digital-Signal
Processing on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {3},
pages = {23:1--23:22},
year = {2016},
url = {https://doi.org/10.1145/2800789},
doi = {10.1145/2800789},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/StittSC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TangK16,
author = {Qing Y. Tang and
Mohammed A. S. Khalid},
title = {Acceleration of k-Means Algorithm Using Altera {SDK} for OpenCL},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {6:1--6:19},
year = {2016},
url = {https://doi.org/10.1145/2964910},
doi = {10.1145/2964910},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TangK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WegleyYZ16,
author = {Evan Wegley and
Yanhua Yi and
Qinhai Zhang},
title = {Application of Specific Delay Window Routing for Timing Optimization
in {FPGA} Designs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {29:1--29:22},
year = {2016},
url = {https://doi.org/10.1145/2892640},
doi = {10.1145/2892640},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WegleyYZ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WilsonS16,
author = {David Wilson and
Greg Stitt},
title = {The Unified Accumulator Architecture: {A} Configurable, Portable,
and Extensible Floating-Point Accumulator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {3},
pages = {21:1--21:23},
year = {2016},
url = {https://doi.org/10.1145/2809432},
doi = {10.1145/2809432},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WilsonS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WintersteinBC16,
author = {Felix J. Winterstein and
Samuel R. Bayliss and
George A. Constantinides},
title = {Separation Logic for High-Level Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {10:1--10:23},
year = {2016},
url = {https://doi.org/10.1145/2836169},
doi = {10.1145/2836169},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WintersteinBC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WongBR16,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor
Memory System},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {7:1--7:22},
year = {2016},
url = {https://doi.org/10.1145/2974022},
doi = {10.1145/2974022},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WongBR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WulfGG16,
author = {Nicholas Wulf and
Alan D. George and
Ann Gordon{-}Ross},
title = {A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace
Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {1:1--1:29},
year = {2016},
url = {https://doi.org/10.1145/2888400},
doi = {10.1145/2888400},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WulfGG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/XuJDSL16,
author = {Jinwei Xu and
Jingfei Jiang and
Yong Dou and
Xiaolong Shen and
Zhiqiang Liu},
title = {Coarse-Grained Architecture for Fingerprint Matching},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {12:1--12:15},
year = {2016},
url = {https://doi.org/10.1145/2791296},
doi = {10.1145/2791296},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/XuJDSL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YuBS16,
author = {Ting Yu and
Chris P. Bradley and
Oliver Sinnen},
title = {ODoST: Automatic Hardware Acceleration for Biomedical Model Integration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {27:1--27:24},
year = {2016},
url = {https://doi.org/10.1145/2870639},
doi = {10.1145/2870639},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/YuBS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZaidiG16,
author = {Ali Mustafa Zaidi and
David J. Greaves},
title = {Value State Flow Graph: {A} Dataflow Compiler {IR} for Accelerating
Control-Intensive Code in Spatial Hardware},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {14:1--14:22},
year = {2016},
url = {https://doi.org/10.1145/2807702},
doi = {10.1145/2807702},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZaidiG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Zain-ul-AbdinS16,
author = {Zain{-}ul{-}Abdin and
Bertil Svensson},
title = {A Retargetable Compilation Framework for Heterogeneous Reconfigurable
Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {24:1--24:22},
year = {2016},
url = {https://doi.org/10.1145/2843946},
doi = {10.1145/2843946},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Zain-ul-AbdinS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangCL16,
author = {Jianfeng Zhang and
Paul Chow and
Hengzhu Liu},
title = {CORDIC-Based Enhanced Systolic Array Architecture for {QR} Decomposition},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {2},
pages = {9:1--9:22},
year = {2016},
url = {https://doi.org/10.1145/2827700},
doi = {10.1145/2827700},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangCL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZienerBBDMSTVW16,
author = {Daniel Ziener and
Florian Bauer and
Andreas Becher and
Christopher Dennl and
Klaus Meyer{-}Wegener and
Ute Sch{\"{u}}rfeld and
J{\"{u}}rgen Teich and
J{\"{o}}rg{-}Stephan Vogt and
Helmut Weber},
title = {FPGA-Based Dynamically Reconfigurable {SQL} Query Processing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {25:1--25:24},
year = {2016},
url = {https://doi.org/10.1145/2845087},
doi = {10.1145/2845087},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZienerBBDMSTVW16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/0001SK15,
author = {Anup Das and
Amit Kumar Singh and
Akash Kumar},
title = {Execution Trace-Driven Energy-Reliability Optimization for Multimedia
MPSoCs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {18:1--18:19},
year = {2015},
url = {https://doi.org/10.1145/2665071},
doi = {10.1145/2665071},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/0001SK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/0001VK15,
author = {Anup Das and
Shyamsundar Venkataraman and
Akash Kumar},
title = {Autonomous Soft-Error Tolerance of {FPGA} Configuration Bits},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {12:1--12:17},
year = {2015},
url = {https://doi.org/10.1145/2629580},
doi = {10.1145/2629580},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/0001VK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BaiAG15,
author = {Yuhui Bai and
Syed Zahid Ahmed and
Bertrand Granado},
title = {{ARC} 2014: Towards a Fast {FPGA} Implementation of a Heap-Based Priority
Queue for Image Coding Using a Parallel Index-Aware Tree},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {8:1--8:16},
year = {2015},
url = {https://doi.org/10.1145/2766454},
doi = {10.1145/2766454},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BaiAG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BhasinDGH15,
author = {Shivam Bhasin and
Jean{-}Luc Danger and
Sylvain Guilley and
Wei He},
title = {Exploiting {FPGA} Block Memories for Protected Cryptographic Implementations},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {16:1--16:16},
year = {2015},
url = {https://doi.org/10.1145/2629552},
doi = {10.1145/2629552},
timestamp = {Thu, 25 Jul 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BhasinDGH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BiedermannHI15,
author = {Alexander Biedermann and
Sorin A. Huss and
Adeel Israr},
title = {Safe Dynamic Reshaping of Reconfigurable MPSoC Embedded Systems for
Self-Healing and Self-Adaption Purposes},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {4},
pages = {26:1--26:22},
year = {2015},
url = {https://doi.org/10.1145/2700416},
doi = {10.1145/2700416},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BiedermannHI15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ButlerS15,
author = {Jon T. Butler and
Tsutomu Sasao},
title = {High-Speed Hardware Partition Generation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {28:1--28:17},
year = {2015},
url = {https://doi.org/10.1145/2629472},
doi = {10.1145/2629472},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ButlerS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CardosoDM15,
author = {Jo{\~{a}}o M. P. Cardoso and
Pedro C. Diniz and
Katherine (Compton) Morrow},
title = {Guest Editorial {FPL} 2013},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {8:1--8:2},
year = {2015},
url = {https://doi.org/10.1145/2737805},
doi = {10.1145/2737805},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CardosoDM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CarloGPRT15,
author = {Stefano Di Carlo and
Giulio Gambardella and
Paolo Prinetto and
Daniele Rolfo and
Pascal Trotta},
title = {{SATTA:} {A} Self-Adaptive Temperature-Based {TDF} Awareness Methodology
for Dynamically Reconfigurable FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {1},
pages = {1:1--1:22},
year = {2015},
url = {https://doi.org/10.1145/2659001},
doi = {10.1145/2659001},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/CarloGPRT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChauNEMCL15,
author = {Thomas C. P. Chau and
Xinyu Niu and
Alison Eele and
Jan M. Maciejowski and
Peter Y. K. Cheung and
Wayne Luk},
title = {Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable
Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {36:1--36:17},
year = {2015},
url = {https://doi.org/10.1145/2629469},
doi = {10.1145/2629469},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChauNEMCL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CookeFBS15,
author = {Patrick Cooke and
Jeremy Fowers and
Greg Brown and
Greg Stitt},
title = {A Tradeoff Analysis of FPGAs, GPUs, and Multicores for Sliding-Window
Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {1},
pages = {2:1--2:24},
year = {2015},
url = {https://doi.org/10.1145/2659000},
doi = {10.1145/2659000},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CookeFBS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DavidsonVHBS15,
author = {Tom Davidson and
Elias Vansteenkiste and
Karel Heyse and
Karel Bruneel and
Dirk Stroobandt},
title = {Identification of Dynamic Circuit Specialization Opportunities in
{RTL} Code},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {1},
pages = {4:1--4:24},
year = {2015},
url = {https://doi.org/10.1145/2629640},
doi = {10.1145/2629640},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DavidsonVHBS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DhawanD15,
author = {Udit Dhawan and
Andr{\'{e}} DeHon},
title = {Area-Efficient Near-Associative Memories on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {30:1--30:22},
year = {2015},
url = {https://doi.org/10.1145/2629471},
doi = {10.1145/2629471},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DhawanD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DobaiS15,
author = {Roland Dobai and
Luk{\'{a}}s Sekanina},
title = {Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable
Hardware},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {20:1--20:24},
year = {2015},
url = {https://doi.org/10.1145/2700414},
doi = {10.1145/2700414},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DobaiS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DuarteB15,
author = {Rui Policarpo Duarte and
Christos{-}Savvas Bouganis},
title = {{ARC} 2014 Over-Clocking {KLT} Designs on FPGAs under Process, Voltage,
and Temperature Variation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {7:1--7:17},
year = {2015},
url = {https://doi.org/10.1145/2818380},
doi = {10.1145/2818380},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DuarteB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FerreiraRSNWC15,
author = {Ricardo S. Ferreira and
Luciana Rocha and
Andr{\'{e}} G. Santos and
Jos{\'{e}} Augusto Miranda Nacif and
Stephan Wong and
Luigi Carro},
title = {A Runtime {FPGA} Placement and Routing Using Low-Complexity Graph
Traversal},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {9:1--9:16},
year = {2015},
url = {https://doi.org/10.1145/2660775},
doi = {10.1145/2660775},
timestamp = {Fri, 04 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/FerreiraRSNWC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GanFLYXHZY15,
author = {Lin Gan and
Haohuan Fu and
Wayne Luk and
Chao Yang and
Wei Xue and
Xiaomeng Huang and
Youhui Zhang and
Guangwen Yang},
title = {Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable
Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {11:1--11:16},
year = {2015},
url = {https://doi.org/10.1145/2629581},
doi = {10.1145/2629581},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GanFLYXHZY15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GiraldoWL15,
author = {Juan Fernando Eusse Giraldo and
Christopher Williams and
Rainer Leupers},
title = {CoEx: {A} Novel Profiling-Based Algorithm/Architecture Co-Exploration
for {ASIP} Design},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {17:1--17:16},
year = {2015},
url = {https://doi.org/10.1145/2629563},
doi = {10.1145/2629563},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GiraldoWL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GoehringerSCB15,
author = {Diana Goehringer and
Marco D. Santambrogio and
Jo{\~{a}}o M. P. Cardoso and
Koen Bertels},
title = {Guest Editorial {ARC} 2014},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {5:1--5:2},
year = {2015},
url = {https://doi.org/10.1145/2831431},
doi = {10.1145/2831431},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GoehringerSCB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GojmanNMHD15,
author = {Benjamin Gojman and
Sirisha Nalmela and
Nikil Mehta and
Nicholas Howarth and
Andr{\'{e}} DeHon},
title = {{GROK-LAB:} Generating Real On-chip Knowledge for Intra-cluster Delays
Using Timing Extraction},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {32:1--32:23},
year = {2015},
url = {https://doi.org/10.1145/2597889},
doi = {10.1145/2597889},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GojmanNMHD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HeyseBFSKP15,
author = {Karel Heyse and
Jente Basteleus and
Brahim Al Farisi and
Dirk Stroobandt and
Oliver Kadlcek and
Oliver Pell},
title = {On the Impact of Replacing Low-Speed Configuration Buses on FPGAs
with the Chip's Internal Configuration Infrastructure},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {6:1--6:18},
year = {2015},
url = {https://doi.org/10.1145/2700835},
doi = {10.1145/2700835},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HeyseBFSKP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HuangLCCXCBA15,
author = {Qijing Huang and
Ruolong Lian and
Andrew Canis and
Jongsok Choi and
Ryan Xi and
Nazanin Calagar and
Stephen Dean Brown and
Jason Helge Anderson},
title = {The Effect of Compiler Optimizations on High-Level Synthesis-Generated
Hardware},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {14:1--14:26},
year = {2015},
url = {https://doi.org/10.1145/2629547},
doi = {10.1145/2629547},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HuangLCCXCBA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/IstvanABV15,
author = {Zsolt Istv{\'{a}}n and
Gustavo Alonso and
Michaela Blott and
Kees A. Vissers},
title = {A Hash Table for Line-Rate Data Processing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {13:1--13:15},
year = {2015},
url = {https://doi.org/10.1145/2629582},
doi = {10.1145/2629582},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/IstvanABV15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/IturbeBHETA15,
author = {Xabier Iturbe and
Khaled Benkrid and
Chuan Hong and
Ali Ebrahim and
Raul Torrego and
Tughrul Arslan},
title = {Microkernel Architecture and Hardware Abstraction Layer of a Reliable
Reconfigurable Real-Time Operating System {(R3TOS)}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {1},
pages = {5:1--5:35},
year = {2015},
url = {https://doi.org/10.1145/2629639},
doi = {10.1145/2629639},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/IturbeBHETA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JacobsenRHK15,
author = {Matthew Jacobsen and
Dustin Richmond and
Matthew Hogains and
Ryan Kastner},
title = {{RIFFA} 2.1: {A} Reusable Integration Framework for {FPGA} Accelerators},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {4},
pages = {22:1--22:23},
year = {2015},
url = {https://doi.org/10.1145/2815631},
doi = {10.1145/2815631},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JacobsenRHK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JinB15,
author = {Zheming Jin and
Jason D. Bakos},
title = {Memory Interface Design for 3D Stencil Kernels on a Massively Parallel
Memory System},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {4},
pages = {24:1--24:24},
year = {2015},
url = {https://doi.org/10.1145/2800788},
doi = {10.1145/2800788},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JinB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KirchgessnerGS15,
author = {Robert Kirchgessner and
Alan D. George and
Greg Stitt},
title = {Low-Overhead {FPGA} Middleware for Application Portability and Productivity},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {4},
pages = {21:1--21:22},
year = {2015},
url = {https://doi.org/10.1145/2746404},
doi = {10.1145/2746404},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KirchgessnerGS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LlamoccaP15,
author = {Daniel Llamocca and
Marios S. Pattichis},
title = {Dynamic Energy, Performance, and Accuracy Optimization and Management
Using Automatically Generated Constraints for Separable 2D {FIR} Filtering
for Digital Video Processing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {31:1--31:30},
year = {2015},
url = {https://doi.org/10.1145/2629623},
doi = {10.1145/2629623},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LlamoccaP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MahramH15,
author = {Atabak Mahram and
Martin C. Herbordt},
title = {{NCBI} {BLASTP} on High-Performance Reconfigurable Computing Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {33:1--33:20},
year = {2015},
url = {https://doi.org/10.1145/2629691},
doi = {10.1145/2629691},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MahramH15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MillerVGB15,
author = {Bailey Miller and
Frank Vahid and
Tony Givargis and
Philip Brisk},
title = {Graph-Based Approaches to Placement of Processing Element Networks
on FPGAs for Physical Model Simulation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {37:1--37:22},
year = {2015},
url = {https://doi.org/10.1145/2629521},
doi = {10.1145/2629521},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MillerVGB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MurrayWLLB15,
author = {Kevin E. Murray and
Scott Whitty and
Suya Liu and
Jason Luu and
Vaughn Betz},
title = {Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap
between Academic and Commercial {CAD}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {10:1--10:18},
year = {2015},
url = {https://doi.org/10.1145/2629579},
doi = {10.1145/2629579},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MurrayWLLB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NiuCJLLP15,
author = {Xinyu Niu and
Thomas C. P. Chau and
Qiwei Jin and
Wayne Luk and
Qiang Liu and
Oliver Pell},
title = {Automating Elimination of Idle Functions by Runtime Reconfiguration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {15:1--15:28},
year = {2015},
url = {https://doi.org/10.1145/2700415},
doi = {10.1145/2700415},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NiuCJLLP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ParkD15,
author = {Joonseok Park and
Pedro C. Diniz},
title = {Program-Invariant Checking for Soft-Error Detection using Reconfigurable
Hardware},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {1:1--1:13},
year = {2015},
url = {https://doi.org/10.1145/2751563},
doi = {10.1145/2751563},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ParkD15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PaulinoFC15,
author = {Nuno Miguel Cardanha Paulino and
Jo{\~{a}}o Canas Ferreira and
Jo{\~{a}}o M. P. Cardoso},
title = {A Reconfigurable Architecture for Binary Acceleration of Loops with
Memory Accesses},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {29:1--29:20},
year = {2015},
url = {https://doi.org/10.1145/2629468},
doi = {10.1145/2629468},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PaulinoFC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/QuinnRCGWMSNHJJ15,
author = {Heather M. Quinn and
Diane Roussel{-}Dupre and
Michael P. Caffrey and
Paul S. Graham and
Michael J. Wirthlin and
Keith Morgan and
Anthony Salazar and
Tony Nelson and
William Howes and
Darrel Eric Johnson and
Jonathan M. Johnson and
Brian H. Pratt and
Nathan Rollins and
Jim Krone},
title = {The Cibola Flight Experiment},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {1},
pages = {3:1--3:22},
year = {2015},
url = {https://doi.org/10.1145/2629556},
doi = {10.1145/2629556},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/QuinnRCGWMSNHJJ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RenLYHW15,
author = {Yu Ren and
Leibo Liu and
Shouyi Yin and
Jie Han and
Shaojun Wei},
title = {Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum
Flow Algorithm},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {3},
pages = {19:1--19:24},
year = {2015},
url = {https://doi.org/10.1145/2700417},
doi = {10.1145/2700417},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RenLYHW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SasdrichG15,
author = {Pascal Sasdrich and
Tim G{\"{u}}neysu},
title = {Implementing Curve25519 for Side-Channel-Protected Elliptic Curve
Cryptography},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {3:1--3:15},
year = {2015},
url = {https://doi.org/10.1145/2700834},
doi = {10.1145/2700834},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SasdrichG15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SciclunaB15,
author = {Neil Scicluna and
Christos{-}Savvas Bouganis},
title = {{ARC} 2014: {A} Multidimensional FPGA-Based Parallel {DBSCAN} Architecture},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {2:1--2:15},
year = {2015},
url = {https://doi.org/10.1145/2724722},
doi = {10.1145/2724722},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SciclunaB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShiBC15,
author = {Kan Shi and
David Boland and
George A. Constantinides},
title = {Imprecise Datapath Design: An Overclocking Approach},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {6:1--6:23},
year = {2015},
url = {https://doi.org/10.1145/2629527},
doi = {10.1145/2629527},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ShiBC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SwierczynskiMOP15,
author = {Pawel Swierczynski and
Amir Moradi and
David F. Oswald and
Christof Paar},
title = {Physical Security Evaluation of the Bitstream Encryption Mechanism
of Altera Stratix {II} and Stratix {III} FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {34:1--34:23},
year = {2015},
url = {https://doi.org/10.1145/2629462},
doi = {10.1145/2629462},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SwierczynskiMOP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TanZWZ15,
author = {Guangming Tan and
Chunming Zhang and
Wendi Wang and
Peiheng Zhang},
title = {SuperDragon: {A} Heterogeneous Parallel System for Accelerating 3D
Reconstruction of Cryo-Electron Microscopy Images},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {4},
pages = {25:1--25:22},
year = {2015},
url = {https://doi.org/10.1145/2740966},
doi = {10.1145/2740966},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TanZWZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Thomas15,
author = {David B. Thomas},
title = {The Table-Hadamard {GRNG:} An Area-Efficient {FPGA} Gaussian Random
Number Generator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {4},
pages = {23:1--23:22},
year = {2015},
url = {https://doi.org/10.1145/2629607},
doi = {10.1145/2629607},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Thomas15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/VliegenMV15,
author = {Jo Vliegen and
Nele Mentens and
Ingrid Verbauwhede},
title = {Secure, Remote, Dynamic Reconfiguration of FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {4},
pages = {35:1--35:19},
year = {2015},
url = {https://doi.org/10.1145/2629423},
doi = {10.1145/2629423},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/VliegenMV15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WoodsAT15,
author = {Louis Woods and
Gustavo Alonso and
Jens Teubner},
title = {Parallelizing Data Processing on FPGAs with Shifter Lists},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {8},
number = {2},
pages = {7:1--7:22},
year = {2015},
url = {https://doi.org/10.1145/2629551},
doi = {10.1145/2629551},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WoodsAT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangCL15,
author = {Jianfeng Zhang and
Paul Chow and
Hengzhu Liu},
title = {An Enhanced Adaptive Recoding Rotation {CORDIC}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {1},
pages = {4:1--4:25},
year = {2015},
url = {https://doi.org/10.1145/2812813},
doi = {10.1145/2812813},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangCL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AbdelfattahB14,
author = {Mohamed S. Abdelfattah and
Vaughn Betz},
title = {Networks-on-Chip for FPGAs: Hard, Soft or Mixed?},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {20:1--20:22},
year = {2014},
url = {https://doi.org/10.1145/2629442},
doi = {10.1145/2629442},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AbdelfattahB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AgneHLPP14,
author = {Andreas Agne and
Markus Happe and
Achim L{\"{o}}sch and
Christian Plessl and
Marco Platzner},
title = {Self-Awareness as a Model for Designing and Operating Heterogeneous
Multicores},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {13:1--13:18},
year = {2014},
url = {https://doi.org/10.1145/2617596},
doi = {10.1145/2617596},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/AgneHLPP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AndersonC14,
author = {Jason Helge Anderson and
Kiyoung Choi},
title = {Introduction to the Special Issue on the 11\({}^{\mbox{th}}\) International
Conference on Field-Programmable Technology (FPT'12)},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {18:1--18:2},
year = {2014},
url = {https://doi.org/10.1145/2655712},
doi = {10.1145/2655712},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AndersonC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Becker14,
author = {Tobias Becker},
title = {Introduction to the {TRETS} Special Section on the Workshop on Self-Awareness
in Reconfigurable Computing Systems (SRCS'12)},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {11:1--11:2},
year = {2014},
url = {https://doi.org/10.1145/2611564},
doi = {10.1145/2611564},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Becker14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BeckhoffKT14,
author = {Christian Beckhoff and
Dirk Koch and
Jim T{\o}rresen},
title = {Design Tools for Implementing Self-Aware and Fault-Tolerant Systems
on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {14:1--14:23},
year = {2014},
url = {https://doi.org/10.1145/2617597},
doi = {10.1145/2617597},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BeckhoffKT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BruggerHB14,
author = {Christian Brugger and
Dominic Hillenbrand and
Matthias Norbert Balzer},
title = {{RIVER:} Reconfigurable Flow and Fabric for Real-Time Signal Processing
on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {24:1--24:16},
year = {2014},
url = {https://doi.org/10.1145/2655238},
doi = {10.1145/2655238},
timestamp = {Tue, 31 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BruggerHB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CheahBFM14,
author = {Hui Yan Cheah and
Fredrik Brosser and
Suhaib A. Fahmy and
Douglas L. Maskell},
title = {The iDEA {DSP} Block-Based Soft Processor for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {19:1--19:23},
year = {2014},
url = {https://doi.org/10.1145/2629443},
doi = {10.1145/2629443},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CheahBFM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenM14,
author = {Liang Chen and
Tulika Mitra},
title = {Graph Minor Approach for Application Mapping on CGRAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {21:1--21:25},
year = {2014},
url = {https://doi.org/10.1145/2655242},
doi = {10.1145/2655242},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChenM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ClementeBRAS14,
author = {Juan Antonio Clemente and
Ivan Beretta and
Vincenzo Rana and
David Atienza and
Donatella Sciuto},
title = {A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable
Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {9:1--9:27},
year = {2014},
url = {https://doi.org/10.1145/2611562},
doi = {10.1145/2611562},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ClementeBRAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuilletLGRGD14,
author = {S{\'{e}}bastien Guillet and
Florent de Lamotte and
Nicolas Le Griguer and
{\'{E}}ric Rutten and
Guy Gogniat and
Jean{-}Philippe Diguet},
title = {Extending {UML/MARTE} to Support Discrete Controller Synthesis, Application
to Reconfigurable Systems-on-Chip Modeling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {27:1--27:17},
year = {2014},
url = {https://doi.org/10.1145/2629628},
doi = {10.1145/2629628},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GuilletLGRGD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HoangF14,
author = {Anh{-}Tuan Hoang and
Takeshi Fujino},
title = {Intra-Masking Dual-Rail Memory on {LUT} Implementation for SCA-Resistant
{AES} on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {10:1--10:19},
year = {2014},
url = {https://doi.org/10.1145/2617595},
doi = {10.1145/2617595},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HoangF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/IskanderPC14,
author = {Yousef Iskander and
Cameron D. Patterson and
Stephen D. Craven},
title = {High-Level Abstractions and Modular Debugging for {FPGA} Design Validation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {1},
pages = {2:1--2:22},
year = {2014},
url = {https://doi.org/10.1145/2567662},
doi = {10.1145/2567662},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/IskanderPC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ItturietNFMC14,
author = {F{\'{a}}bio P. Itturriet and
Gabriel L. Nazar and
Ronaldo Rodrigues Ferreira and
{\'{A}}lvaro Freitas Moreira and
Luigi Carro},
title = {Adaptive Parallelism Exploitation under Physical and Real-Time Constraints
for Resilient Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {25:1--25:17},
year = {2014},
url = {https://doi.org/10.1145/2556943},
doi = {10.1145/2556943},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/ItturietNFMC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JSC14,
author = {Soumya J. and
Ashish Sharma and
Santanu Chattopadhyay},
title = {Multi-Application Network-on-Chip Design using Global Mapping and
Local Reconfiguration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {7:1--7:24},
year = {2014},
url = {https://doi.org/10.1145/2556944},
doi = {10.1145/2556944},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/JSC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JinM14,
author = {Minxi Jin and
Tsutomu Maruyama},
title = {Fast and Accurate Stereo Vision System on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {1},
pages = {3:1--3:24},
year = {2014},
url = {https://doi.org/10.1145/2567659},
doi = {10.1145/2567659},
timestamp = {Thu, 25 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JinM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KimAL14,
author = {Lok{-}Won Kim and
Sameh W. Asaad and
Ralph Linsker},
title = {A Fully Pipelined {FPGA} Architecture of a Factored Restricted Boltzmann
Machine Artificial Neural Network},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {1},
pages = {5:1--5:23},
year = {2014},
url = {https://doi.org/10.1145/2539125},
doi = {10.1145/2539125},
timestamp = {Wed, 25 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KimAL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KimCCKRK14,
author = {Changmoo Kim and
Moo{-}Kyoung Chung and
Yeon{-}Gon Cho and
Mario Konijnenburg and
Soojung Ryu and
Jeongwook Kim},
title = {{ULP-SRP:} Ultra Low-Power Samsung Reconfigurable Processor for Biomedical
Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {22:1--22:15},
year = {2014},
url = {https://doi.org/10.1145/2629610},
doi = {10.1145/2629610},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KimCCKRK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KornarosP14,
author = {George Kornaros and
Dionisios N. Pnevmatikatos},
title = {Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {1},
pages = {1:1--1:26},
year = {2014},
url = {https://doi.org/10.1145/2567658},
doi = {10.1145/2567658},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KornarosP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LaForestLOLS14,
author = {Charles Eric LaForest and
Zimo Li and
Tristan O'rourke and
Ming G. Liu and
J. Gregory Steffan},
title = {Composing Multi-Ported Memories on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {16:1--16:23},
year = {2014},
url = {https://doi.org/10.1145/2629629},
doi = {10.1145/2629629},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LaForestLOLS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LamCS14,
author = {Siew Kei Lam and
Christopher T. Clarke and
Thambipillai Srikanthan},
title = {Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {26:1--26:15},
year = {2014},
url = {https://doi.org/10.1145/2655240},
doi = {10.1145/2655240},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LamCS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LeiGDMX14,
author = {Yuanwu Lei and
Lei Guo and
Yong Dou and
Sheng Ma and
Jinbo Xu},
title = {{FPGA} Implementation of a Special-Purpose {VLIW} Structure for Double-Precision
Elementary Function},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {8:1--8:21},
year = {2014},
url = {https://doi.org/10.1145/2617594},
doi = {10.1145/2617594},
timestamp = {Thu, 15 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LeiGDMX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuuGWSYNNWLAKARB14,
author = {Jason Luu and
Jeffrey Goeders and
Michael Wainberg and
Andrew Somerville and
Thien Yu and
Konstantin Nasartschuk and
Miad Nasr and
Sen Wang and
Tim Liu and
Nooruddin Ahmed and
Kenneth B. Kent and
Jason Helge Anderson and
Jonathan Rose and
Vaughn Betz},
title = {{VTR} 7.0: Next Generation Architecture and {CAD} System for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {6:1--6:30},
year = {2014},
url = {https://doi.org/10.1145/2617593},
doi = {10.1145/2617593},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LuuGWSYNNWLAKARB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NiuJLW14,
author = {Xinyu Niu and
Qiwei Jin and
Wayne Luk and
Stephen Weston},
title = {A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference
Applications in Reconfigurable Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {15:1--15:19},
year = {2014},
url = {https://doi.org/10.1145/2617598},
doi = {10.1145/2617598},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NiuJLW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PaneratiMCSTS14,
author = {Jacopo Panerati and
Martina Maggio and
Matteo Carminati and
Filippo Sironi and
Marco Triverio and
Marco D. Santambrogio},
title = {Coordination of Independent Loops in Self-Adaptive Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {12:1--12:16},
year = {2014},
url = {https://doi.org/10.1145/2611563},
doi = {10.1145/2611563},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PaneratiMCSTS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PengSMZC14,
author = {Yuanxi Peng and
Manuel Salda{\~{n}}a and
Christopher A. Madill and
Xiaofeng Zou and
Paul Chow},
title = {Benefits of Adding Hardware Support for Broadcast and Reduce Operations
in MPSoC Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {17:1--17:23},
year = {2014},
url = {https://doi.org/10.1145/2629470},
doi = {10.1145/2629470},
timestamp = {Mon, 13 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/PengSMZC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/UluselNBR14,
author = {Onur Ulusel and
Kumud Nepal and
R. Iris Bahar and
Sherief Reda},
title = {Fast Design Exploration for Performance, Power and Accuracy Tradeoffs
in FPGA-Based Accelerators},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {1},
pages = {4:1--4:22},
year = {2014},
url = {https://doi.org/10.1145/2567661},
doi = {10.1145/2567661},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/UluselNBR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/VorosG14,
author = {Nikolaos S. Voros and
Guy Gogniat},
title = {Introduction to the Special Issue on the 7th International Workshop
on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'12)},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {23:1},
year = {2014},
url = {https://doi.org/10.1145/2655710},
doi = {10.1145/2655710},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/VorosG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AnanthanV13,
author = {T. Ananthan and
M. V. Vaidyan},
title = {A Reconfigurable Parallel Hardware Implementation of the Self-Tuning
Regulator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {4},
pages = {17:1--17:21},
year = {2013},
url = {https://doi.org/10.1145/2535934},
doi = {10.1145/2535934},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AnanthanV13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BachirD13,
author = {Tarek Ould{-}Bachir and
Jean{-}Pierre David},
title = {Self-Alignment Schemes for the Implementation of Addition-Related
Floating-Point Operators},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {1},
pages = {1:1--1:21},
year = {2013},
url = {https://doi.org/10.1145/2457443.2457444},
doi = {10.1145/2457443.2457444},
timestamp = {Mon, 31 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BachirD13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Ben-AsherMR13,
author = {Yosi Ben{-}Asher and
Ron Meldiner and
Nadav Rotem},
title = {Optimizing Wait States in the Synthesis of Memory References with
Unpredictable Latencies},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {4},
pages = {19:1--19:9},
year = {2013},
url = {https://doi.org/10.1145/2535936},
doi = {10.1145/2535936},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Ben-AsherMR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DasW13,
author = {Joydip Das and
Steven J. E. Wilton},
title = {Towards development of an analytical model relating {FPGA} architecture
parameters to routability},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {2},
pages = {10:1--10:24},
year = {2013},
url = {https://doi.org/10.1145/2499625.2499627},
doi = {10.1145/2499625.2499627},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DasW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DinechinELP13,
author = {Florent de Dinechin and
Pedro Echeverr{\'{\i}}a and
Marisa L{\'{o}}pez{-}Vallejo and
Bogdan Pasca},
title = {Floating-Point Exponentiation Units for Reconfigurable Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {1},
pages = {4:1--4:15},
year = {2013},
url = {https://doi.org/10.1145/2457443.2457447},
doi = {10.1145/2457443.2457447},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DinechinELP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GanegedaraP13,
author = {Thilan Ganegedara and
Viktor K. Prasanna},
title = {A comprehensive performance analysis of virtual routers on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {2},
pages = {9:1--9:21},
year = {2013},
url = {https://dl.acm.org/citation.cfm?id=2492187},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GanegedaraP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GharibianSJC13,
author = {Farnaz Gharibian and
Lesley Shannon and
Peter Jamieson and
Kevin Chung},
title = {Analyzing System-Level Information's Correlation to {FPGA} Placement},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {3},
pages = {15:1--15:21},
year = {2013},
url = {https://doi.org/10.1145/2501985},
doi = {10.1145/2501985},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GharibianSJC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GoehringerC13,
author = {Diana Goehringer and
Ren{\'{e}} Cumplido},
title = {Introduction to the special section on 19th reconfigurable architectures
workshop {(RAW} 2012)},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {2},
pages = {6:1},
year = {2013},
url = {https://doi.org/10.1145/2499625.2499626},
doi = {10.1145/2499625.2499626},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GoehringerC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HeisswolfZWKWTHB13,
author = {Jan Heisswolf and
Aurang Zaib and
Andreas Weichslgartner and
Ralf K{\"{o}}nig and
Thomas Wild and
J{\"{u}}rgen Teich and
Andreas Herkersdorf and
J{\"{u}}rgen Becker},
title = {Virtual networks - distributed communication resource management},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {2},
pages = {8:1--8:14},
year = {2013},
url = {https://dl.acm.org/citation.cfm?id=2492186},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HeisswolfZWKWTHB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HormigoCOB13,
author = {Javier Hormigo and
Gabriel Caffarena and
Juan P. Oliver and
Eduardo I. Boemo},
title = {Self-Reconfigurable Constant Multiplier for {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {3},
pages = {14:1--14:17},
year = {2013},
url = {https://doi.org/10.1145/2490830},
doi = {10.1145/2490830},
timestamp = {Thu, 26 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/HormigoCOB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HuangH13,
author = {Chun{-}Hsian Huang and
Pao{-}Ann Hsiung},
title = {Virtualizable hardware/software design infrastructure for dynamically
partially reconfigurable systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {2},
pages = {11:1--11:18},
year = {2013},
url = {https://doi.org/10.1145/2499625.2499628},
doi = {10.1145/2499625.2499628},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HuangH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LeowAL13,
author = {Yoon Kah Leow and
Ali Akoglu and
Susan Lysecky},
title = {An Analytical Model for Evaluating Static Power of Homogeneous {FPGA}
Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {4},
pages = {18:1--18:22},
year = {2013},
url = {https://doi.org/10.1145/2535935},
doi = {10.1145/2535935},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LeowAL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuRA13,
author = {Hanyu Liu and
Senthilkumar Thoravi Rajavel and
Ali Akoglu},
title = {Integration of Net-Length Factor with Timing- and Routability-Driven
Clustering Algorithms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {3},
pages = {12:1--12:21},
year = {2013},
url = {https://doi.org/10.1145/2517324},
doi = {10.1145/2517324},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuRA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MeeuwsOGSNB13,
author = {Roel Meeuws and
Sayyed Arash Ostadzadeh and
Carlo Galuzzi and
Vlad Mihai Sima and
Razvan Nane and
Koen Bertels},
title = {Quipu: {A} Statistical Model for Predicting Hardware Resources},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {1},
pages = {3:1--3:25},
year = {2013},
url = {https://doi.org/10.1145/2457443.2457446},
doi = {10.1145/2457443.2457446},
timestamp = {Thu, 09 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MeeuwsOGSNB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MehtaCLPPRSYR13,
author = {Gayatri Mehta and
Carson Crawford and
Xiaozhong Luo and
Natalie Parde and
Krunalkumar Patel and
Brandon Rodgers and
Anil Kumar Sistla and
Anil Yadav and
Marc Reisner},
title = {{UNTANGLED:} {A} Game Environment for Discovery of Creative Mapping
Strategies},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {3},
pages = {13:1--13:26},
year = {2013},
url = {https://doi.org/10.1145/2517325},
doi = {10.1145/2517325},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MehtaCLPPRSYR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NeelyBS13,
author = {Christopher E. Neely and
Gordon J. Brebner and
Weijia Shang},
title = {ReShape: Towards a High-Level Approach to Design and Operation of
Modular Reconfigurable Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {1},
pages = {5:1--5:23},
year = {2013},
url = {https://doi.org/10.1145/2457443.2457448},
doi = {10.1145/2457443.2457448},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NeelyBS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PlavecVB13,
author = {Franjo Plavec and
Zvonko G. Vranesic and
Stephen Dean Brown},
title = {Exploiting Task- and Data-Level Parallelism in Streaming Applications
Implemented in FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {4},
pages = {16:1--16:37},
year = {2013},
url = {https://doi.org/10.1145/2535932},
doi = {10.1145/2535932},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PlavecVB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SidiropoulosSFSHB13,
author = {Harry Sidiropoulos and
Kostas Siozios and
Peter Figuli and
Dimitrios Soudris and
Michael H{\"{u}}bner and
J{\"{u}}rgen Becker},
title = {{JITPR:} {A} framework for supporting fast application's implementation
onto FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {2},
pages = {7:1--7:12},
year = {2013},
url = {https://dl.acm.org/citation.cfm?id=2492185},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SidiropoulosSFSHB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangZJB13,
author = {Yan Zhang and
Fan Zhang and
Zheming Jin and
Jason D. Bakos},
title = {An FPGA-Based Accelerator for Frequent Itemset Mining},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {6},
number = {1},
pages = {2:1--2:17},
year = {2013},
url = {https://doi.org/10.1145/2457443.2457445},
doi = {10.1145/2457443.2457445},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangZJB13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AggarwalSGY12,
author = {Vikas Aggarwal and
Greg Stitt and
Alan D. George and
Changil Yoon},
title = {{SCF:} {A} Framework for Task-Level Coordination in Reconfigurable,
Heterogeneous Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {2},
pages = {7:1--7:23},
year = {2012},
url = {https://doi.org/10.1145/2209285.2209286},
doi = {10.1145/2209285.2209286},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AggarwalSGY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CancareBCSS12,
author = {Fabio Cancare and
Davide B. Bartolini and
Matteo Carminati and
Donatella Sciuto and
Marco D. Santambrogio},
title = {On the Evolution of Hardware Circuits via Reconfigurable Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {4},
pages = {22:1--22:22},
year = {2012},
url = {https://doi.org/10.1145/2392616.2392620},
doi = {10.1145/2392616.2392620},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CancareBCSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChengXGLWH12,
author = {Lerong Cheng and
Wenyao Xu and
Fang Gong and
Yan Lin and
Ho{-}Yan Wong and
Lei He},
title = {Statistical Timing and Power Optimization of Architecture and Device
for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {2},
pages = {9:1--9:19},
year = {2012},
url = {https://doi.org/10.1145/2209285.2209288},
doi = {10.1145/2209285.2209288},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChengXGLWH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FeketeKSTVAKT12,
author = {S{\'{a}}ndor P. Fekete and
Tom Kamphans and
Nils Schweer and
Christopher Tessars and
Jan van der Veen and
Josef Angermeier and
Dirk Koch and
J{\"{u}}rgen Teich},
title = {Dynamic Defragmentation of Reconfigurable Devices},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {2},
pages = {8:1--8:20},
year = {2012},
url = {https://doi.org/10.1145/2209285.2209287},
doi = {10.1145/2209285.2209287},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/FeketeKSTVAKT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GantelKMBKLR12,
author = {Laurent Gantel and
Amel Khiar and
Beno{\^{\i}}t Miramond and
Mohamed El Amine Benkhelifa and
Lounis Kessal and
Fabrice Lemonnier and
Jimmy Le Rhun},
title = {Enhancing Reconfigurable Platforms Programmability for Synchronous
Data-Flow Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {14:1--14:16},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362378},
doi = {10.1145/2362374.2362378},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GantelKMBKLR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GasparFBF12,
author = {Lubos Gaspar and
Viktor Fischer and
Lilian Bossuet and
Robert Fouquet},
title = {Secure Extension of {FPGA} General Purpose Processors for Symmetric
Key Cryptography with Partial Reconfiguration Capabilities},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {16:1--16:13},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362380},
doi = {10.1145/2362374.2362380},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GasparFBF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Hubner12,
author = {Michael H{\"{u}}bner},
title = {Introduction to the Special Issue on ReCoSoC 2011},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {11:1},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362375},
doi = {10.1145/2362374.2362375},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Hubner12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JacobsCGGL12,
author = {Adam Jacobs and
Grzegorz Cieslewski and
Alan D. George and
Ann Gordon{-}Ross and
Herman Lam},
title = {Reconfigurable Fault Tolerance: {A} Comprehensive Framework for Reliable
and Adaptive FPGA-Based Space Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {4},
pages = {21:1--21:30},
year = {2012},
url = {https://doi.org/10.1145/2392616.2392619},
doi = {10.1145/2392616.2392619},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JacobsCGGL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KriegGSWBH12,
author = {Armin Krieg and
Johannes Grinschgl and
Christian Steger and
Reinhold Weiss and
Holger Bock and
Josef Haid},
title = {{POWER-MODES:} POWer-EmulatoR- and MOdel-Based DEpendability and Security
Evaluations},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {4},
pages = {19:1--19:21},
year = {2012},
url = {https://doi.org/10.1145/2392616.2392617},
doi = {10.1145/2392616.2392617},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KriegGSWBH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LusalaL12,
author = {Angelo Kuti Lusala and
Jean{-}Didier Legat},
title = {A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {15:1--15:22},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362379},
doi = {10.1145/2362374.2362379},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LusalaL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MartinWKFC12,
author = {Kevin J. M. Martin and
Christophe Wolinski and
Krzysztof Kuchcinski and
Antoine Floch and
Fran{\c{c}}ois Charot},
title = {Constraint Programming Approach to Reconfigurable Processor Extension
Generation and Application Compilation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {2},
pages = {10:1--10:38},
year = {2012},
url = {https://doi.org/10.1145/2209285.2209289},
doi = {10.1145/2209285.2209289},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MartinWKFC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MichailAKTG12,
author = {Harris E. Michail and
George Athanasiou and
Vasilios I. Kelefouras and
George Theodoridis and
Costas E. Goutis},
title = {On the exploitation of a high-throughput {SHA-256} {FPGA} design for
{HMAC}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {1},
pages = {2:1--2:28},
year = {2012},
url = {https://doi.org/10.1145/2133352.2133354},
doi = {10.1145/2133352.2133354},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MichailAKTG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MorganCN12,
author = {Fearghal Morgan and
Seamus Cawley and
David Newell},
title = {Remote {FPGA} Lab for Enhancing Learning of Digital Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {18:1--18:13},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362382},
doi = {10.1145/2362374.2362382},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MorganCN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NabinaN12,
author = {Atukem Nabina and
Jos{\'{e}} Luis N{\'{u}}{\~{n}}ez{-}Y{\'{a}}{\~{n}}ez},
title = {Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based
Platform},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {4},
pages = {20:1--20:22},
year = {2012},
url = {https://doi.org/10.1145/2392616.2392618},
doi = {10.1145/2392616.2392618},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NabinaN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Olivares12,
author = {Joaqu{\'{\i}}n Olivares},
title = {Reconfigurable architecture for {VBSME} with variable pixel precision},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {1},
pages = {3:1--3:11},
year = {2012},
url = {https://doi.org/10.1145/2133352.2133355},
doi = {10.1145/2133352.2133355},
timestamp = {Thu, 12 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/Olivares12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/OstVIMAWMS12,
author = {Luciano Ost and
Sameer Varyani and
Leandro Soares Indrusiak and
Marcelo Mandelli and
Gabriel Marchesan Almeida and
Eduardo W{\"{a}}chter and
Fernando Moraes and
Gilles Sassatelli},
title = {Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {17:1--17:11},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362381},
doi = {10.1145/2362374.2362381},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/OstVIMAWMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShieldDG12,
author = {John Shield and
Jean{-}Philippe Diguet and
Guy Gogniat},
title = {Asymmetric Cache Coherency: Policy Modifications to Improve Multicore
Performance},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {12:1--12:12},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362376},
doi = {10.1145/2362374.2362376},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ShieldDG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SioziosPS12,
author = {Kostas Siozios and
Vasilis F. Pavlidis and
Dimitrios Soudris},
title = {A novel framework for exploring 3-D FPGAs with heterogeneous interconnect
fabric},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {1},
pages = {4:1--4:23},
year = {2012},
url = {https://doi.org/10.1145/2133352.2133356},
doi = {10.1145/2133352.2133356},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SioziosPS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Takano12,
author = {Shigeyuki Takano},
title = {Design and analysis of adaptive processor},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {1},
pages = {5:1--5:34},
year = {2012},
url = {https://doi.org/10.1145/2133352.2133357},
doi = {10.1145/2133352.2133357},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Takano12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ThielmannHK12,
author = {Benjamin Thielmann and
Jens Huthmann and
Andreas Koch},
title = {Memory Latency Hiding by Load Value Speculation for Reconfigurable
Computers},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {3},
pages = {13:1--13:14},
year = {2012},
url = {https://doi.org/10.1145/2362374.2362377},
doi = {10.1145/2362374.2362377},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ThielmannHK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangBR12,
author = {Wei Zhang and
Vaughn Betz and
Jonathan Rose},
title = {Portable and scalable FPGA-based acceleration of a direct linear system
solver},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {1},
pages = {6:1--6:26},
year = {2012},
url = {https://doi.org/10.1145/2133352.2133358},
doi = {10.1145/2133352.2133358},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangBR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZickH12,
author = {Kenneth M. Zick and
John P. Hayes},
title = {Low-cost sensing with ring oscillator arrays for healthier reconfigurable
systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {1},
pages = {1:1--1:26},
year = {2012},
url = {https://doi.org/10.1145/2133352.2133353},
doi = {10.1145/2133352.2133353},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZickH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AggarwalGYYL11,
author = {Vikas Aggarwal and
Alan D. George and
Changil Yoon and
Kishore Yalamanchili and
Herman Lam},
title = {{SHMEM+:} {A} multilevel-PGAS programming model for reconfigurable
supercomputing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {26:1--26:24},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000838},
doi = {10.1145/2000832.2000838},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AggarwalGYYL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BergeronPFD11,
author = {Etienne Bergeron and
Louis{-}David Perron and
Marc Feeley and
Jean{-}Pierre David},
title = {Logarithmic-Time {FPGA} Bitstream Analysis: {A} Step Towards {JIT}
Hardware Compilation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {12:1--12:27},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968503},
doi = {10.1145/1968502.1968503},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BergeronPFD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BolandC11,
author = {David Boland and
George A. Constantinides},
title = {Optimizing memory bandwidth use and performance for matrix-vector
multiplication in iterative methods},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {22:1--22:14},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000834},
doi = {10.1145/2000832.2000834},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BolandC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenA11,
author = {Xiaoheng Chen and
Venkatesh Akella},
title = {Exploiting data-level parallelism for energy-efficient implementation
of {LDPC} decoders and {DCT} on an {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {37:1--37:17},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068723},
doi = {10.1145/2068716.2068723},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChenA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Cheung11,
author = {Peter Y. K. Cheung},
title = {Introduction to special section {FPGA} 2009},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {31:1},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068717},
doi = {10.1145/2068716.2068717},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Cheung11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DemertziDHGW11,
author = {Melina Demertzi and
Pedro C. Diniz and
Mary W. Hall and
Anna C. Gilbert and
Yi Wang},
title = {Domain-Specific Optimization of Signal Recognition Targeting FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {17:1--17:26},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968508},
doi = {10.1145/1968502.1968508},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DemertziDHGW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/EaswaranA11,
author = {Lakshmi Easwaran and
Ali Akoglu},
title = {Net-length-based routability-driven power-aware clustering},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {38:1--38:16},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068724},
doi = {10.1145/2068716.2068724},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/EaswaranA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GaluzziB11,
author = {Carlo Galuzzi and
Koen Bertels},
title = {The Instruction-Set Extension Problem: {A} Survey},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {18:1--18:28},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968509},
doi = {10.1145/1968502.1968509},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GaluzziB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GlaserDHG11,
author = {Johann Glaser and
Markus Damm and
Jan Haase and
Christoph Grimm},
title = {{TR-FSM:} Transition-Based reconfigurable finite state machine},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {23:1--23:14},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000835},
doi = {10.1145/2000832.2000835},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GlaserDHG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HollandGLS11,
author = {Brian Holland and
Alan D. George and
Herman Lam and
Melissa C. Smith},
title = {An analytical model for multilevel performance prediction of Multi-FPGA
systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {27:1--27:28},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000839},
doi = {10.1145/2000832.2000839},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HollandGLS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/InoueYYTMF11,
author = {Hiroaki Inoue and
Junya Yamada and
Hideyuki Yoneda and
Katsumi Togawa and
Masato Motomura and
Koichiro Furuta},
title = {Test compression for dynamically reconfigurable processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {40:1--40:15},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068726},
doi = {10.1145/2068716.2068726},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/InoueYYTMF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KaganovLC11,
author = {Alexander Kaganov and
Asif Lakhany and
Paul Chow},
title = {{FPGA} Acceleration of MultiFactor {CDO} Pricing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {20:1--20:17},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968511},
doi = {10.1145/1968502.1968511},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KaganovLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KenningsVKPF11,
author = {Andrew A. Kennings and
Kristofer Vorwerk and
Arun Kundu and
Val Pevzner and
Andy Fox},
title = {{FPGA} technology mapping with encoded libraries and staged priority
cuts},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {35:1--35:17},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068721},
doi = {10.1145/2068716.2068721},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KenningsVKPF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KoehlerSG11,
author = {Seth Koehler and
Greg Stitt and
Alan D. George},
title = {Platform-aware bottleneck detection for reconfigurable computing applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {30:1--30:28},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000842},
doi = {10.1145/2000832.2000842},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KoehlerSG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LabrecqueJS11,
author = {Martin Labrecque and
Mark C. Jeffrey and
J. Gregory Steffan},
title = {Application-specific signatures for transactional memory in soft processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {21:1--21:14},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000833},
doi = {10.1145/2000832.2000833},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LabrecqueJS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuuKJCYFKR11,
author = {Jason Luu and
Ian Kuon and
Peter Jamieson and
Ted Campbell and
Andy Gean Ye and
Wei Mark Fang and
Kenneth B. Kent and
Jonathan Rose},
title = {{VPR} 5.0: {FPGA} {CAD} and architecture exploration tools with single-driver
routing, heterogeneity and process scaling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {32:1--32:23},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068718},
doi = {10.1145/2068716.2068718},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LuuKJCYFKR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MishchenkoBJJ11,
author = {Alan Mishchenko and
Robert K. Brayton and
Jie{-}Hong R. Jiang and
Stephen Jang},
title = {Scalable don't-care-based logic optimization and resynthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {34:1--34:23},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068720},
doi = {10.1145/2068716.2068720},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MishchenkoBJJ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NakajimaW11,
author = {Mao Nakajima and
Minoru Watanabe},
title = {Fast Optical Reconfiguration of a Nine-Context {DORGA} Using a Speed
Adjustment Control},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {15:1--15:21},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968506},
doi = {10.1145/1968502.1968506},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NakajimaW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/NavaSSHPWR11,
author = {Federico Nava and
Donatella Sciuto and
Marco D. Santambrogio and
Stefan Herbrechtsmeier and
Mario Porrmann and
Ulf Witkowski and
Ulrich R{\"{u}}ckert},
title = {Applying dynamic reconfiguration in the mobile robotics domain: {A}
case study on computer vision algorithms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {29:1--29:22},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000841},
doi = {10.1145/2000832.2000841},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/NavaSSHPWR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ONeillWMZ11,
author = {Shane O'Neill and
Roger F. Woods and
Alan Marshall and
Qi Zhang},
title = {A Scalable and Programmable Modular Traffic Manager Architecture},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {14:1--14:19},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968505},
doi = {10.1145/1968502.1968505},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ONeillWMZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PapadimitriouDH11,
author = {Kyprianos Papadimitriou and
Apostolos Dollas and
Scott Hauck},
title = {Performance of partial reconfiguration in {FPGA} systems: {A} survey
and a cost model},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {36:1--36:24},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068722},
doi = {10.1145/2068716.2068722},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PapadimitriouDH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Parandeh-AfsharNBI11,
author = {Hadi Parandeh{-}Afshar and
Arkosnato Neogy and
Philip Brisk and
Paolo Ienne},
title = {Compressor tree synthesis on commercial high-performance FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {39:1--39:19},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068725},
doi = {10.1145/2068716.2068725},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Parandeh-AfsharNBI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ParvezMKM11,
author = {Husain Parvez and
Zied Marrakchi and
Alp Kili{\c{c}} and
Habib Mehrez},
title = {Application-Specific {FPGA} using heterogeneous logic blocks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {24:1--24:14},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000836},
doi = {10.1145/2000832.2000836},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ParvezMKM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RubinD11,
author = {Raphael Rubin and
Andr{\'{e}} DeHon},
title = {Choose-your-own-adventure routing: Lightweight load-time defect avoidance},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {33:1--33:24},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068719},
doi = {10.1145/2068716.2068719},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RubinD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RupnowUC11,
author = {Kyle Rupnow and
Keith D. Underwood and
Katherine Compton},
title = {Scientific Application Demands on a Reconfigurable Functional Unit
Interface},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {19:1--19:30},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968510},
doi = {10.1145/1968502.1968510},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RupnowUC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ShannonC11,
author = {Lesley Shannon and
Paul Chow},
title = {Leveraging reconfigurability in the hardware/software codesign process},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {28:1--28:27},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000840},
doi = {10.1145/2000832.2000840},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ShannonC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TaiL11,
author = {Tzu{-}Chiang Tai and
Yen{-}Tai Lai},
title = {A Performance-Oriented Algorithm with Consideration on Communication
Cost for Dynamically Reconfigurable {FPGA} Partitioning},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {16:1--16:18},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968507},
doi = {10.1145/1968502.1968507},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TaiL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/VaidyaL11,
author = {Pranav Vaidya and
Jaehwan John Lee},
title = {A Novel Multicontext Coarse-Grained Reconfigurable Architecture {(CGRA)}
For Accelerating Column-Oriented Databases},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {2},
pages = {13:1--13:30},
year = {2011},
url = {https://doi.org/10.1145/1968502.1968504},
doi = {10.1145/1968502.1968504},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/VaidyaL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YanXCGWLH11,
author = {Jing Yan and
Ning{-}Yi Xu and
Xiongfei Cai and
Rui Gao and
Yu Wang and
Rong Luo and
Feng{-}Hsiung Hsu},
title = {An FPGA-based accelerator for LambdaRank in Web search engines},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {3},
pages = {25:1--25:19},
year = {2011},
url = {https://doi.org/10.1145/2000832.2000837},
doi = {10.1145/2000832.2000837},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YanXCGWLH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BadrignansCEGT10,
author = {Beno{\^{\i}}t Badrignans and
David Champagne and
Reouven Elbaz and
Catherine H. Gebotys and
Lionel Torres},
title = {{SARFUM:} Security Architecture for Remote {FPGA} Update and Monitoring},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {2},
pages = {8:1--8:29},
year = {2010},
url = {https://doi.org/10.1145/1754386.1754389},
doi = {10.1145/1754386.1754389},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BadrignansCEGT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BanerjeeBND10,
author = {Sudarshan Banerjee and
Elaheh Bozorgzadeh and
Juanjo Noguera and
Nikil D. Dutt},
title = {Bandwidth Management in Application Mapping for Dynamically Reconfigurable
Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {18:1--18:30},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839488},
doi = {10.1145/1839480.1839488},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BanerjeeBND10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Ben-AsherMR10,
author = {Yosi Ben{-}Asher and
Danny Meisler and
Nadav Rotem},
title = {Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {15:1--15:19},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839485},
doi = {10.1145/1839480.1839485},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Ben-AsherMR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BodilyNWLC10,
author = {John Bodily and
Brent E. Nelson and
Zhaoyi Wei and
Dah{-}Jye Lee and
Jeff Chase},
title = {A Comparison Study on Implementing Optical Flow and Digital Communications
on FPGAs and GPUs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {2},
pages = {6:1--6:22},
year = {2010},
url = {https://doi.org/10.1145/1754386.1754387},
doi = {10.1145/1754386.1754387},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BodilyNWLC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChiuH10,
author = {Matt Chiu and
Martin C. Herbordt},
title = {Molecular Dynamics Simulations on High-Performance Reconfigurable
Computing Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {23:1--23:37},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862653},
doi = {10.1145/1862648.1862653},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChiuH10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CurreriKGHG10,
author = {John Curreri and
Seth Koehler and
Alan D. George and
Brian Holland and
Rafael Garc{\'{\i}}a},
title = {Performance Analysis Framework for High-Level Language Applications
in Reconfigurable Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {1},
pages = {5:1--5:23},
year = {2010},
url = {https://doi.org/10.1145/1661438.1661443},
doi = {10.1145/1661438.1661443},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CurreriKGHG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DrimerGP10,
author = {Saar Drimer and
Tim G{\"{u}}neysu and
Christof Paar},
title = {DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for {AES} on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {1},
pages = {3:1--3:27},
year = {2010},
url = {https://doi.org/10.1145/1661438.1661441},
doi = {10.1145/1661438.1661441},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DrimerGP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DuBoisDBDP10,
author = {David DuBois and
Andrew DuBois and
Thomas Boorman and
Carolyn Connor Davenport and
Steve Poole},
title = {Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer
with Application},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {1},
pages = {2:1--2:31},
year = {2010},
url = {https://doi.org/10.1145/1661438.1661440},
doi = {10.1145/1661438.1661440},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/DuBoisDBDP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuoS10,
author = {Xu Guo and
Patrick Schaumont},
title = {Optimized System-on-Chip Integration of a Programmable {ECC} Coprocessor},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {6:1--6:21},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857933},
doi = {10.1145/1857927.1857933},
timestamp = {Fri, 04 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/GuoS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HemmertU10,
author = {K. Scott Hemmert and
Keith D. Underwood},
title = {Fast, Efficient Floating-Point Adders and Multipliers for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {11:1--11:30},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839481},
doi = {10.1145/1839480.1839481},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HemmertU10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HsiungHSC10,
author = {Pao{-}Ann Hsiung and
Chun{-}Hsian Huang and
Jih{-}Sheng Shen and
Cheng{-}Chi Chiang},
title = {Scheduling and Placement of Hardware/Software Real-Time Relocatable
Tasks in Dynamically Partially Reconfigurable Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {9:1--9:32},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857936},
doi = {10.1145/1857927.1857936},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HsiungHSC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HuangNSSE10,
author = {Miaoqing Huang and
Vikram K. Narayana and
Harald Simmler and
Olivier Serres and
Tarek A. El{-}Ghazawi},
title = {Reconfiguration and Communication-Aware Task Scheduling for High-Performance
Reconfigurable Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {20:1--20:25},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862650},
doi = {10.1145/1862648.1862650},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HuangNSSE10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HuffmireLNIBWSK10,
author = {Ted Huffmire and
Timothy E. Levin and
Thuy D. Nguyen and
Cynthia E. Irvine and
Brett Brotherton and
Gang Wang and
Timothy Sherwood and
Ryan Kastner},
title = {Security Primitives for Reconfigurable Hardware-Based Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {2},
pages = {10:1--10:35},
year = {2010},
url = {https://doi.org/10.1145/1754386.1754391},
doi = {10.1145/1754386.1754391},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HuffmireLNIBWSK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/InoueZOYAIS10,
author = {Kazuki Inoue and
Qian Zhao and
Yasuhiro Okamoto and
Hiroki Yosho and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
title = {A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable
{IP} Core},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {5:1--5:24},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857932},
doi = {10.1145/1857927.1857932},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/InoueZOYAIS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KahoulSCC10,
author = {Asma Kahoul and
Alastair M. Smith and
George A. Constantinides and
Peter Y. K. Cheung},
title = {Efficient Heterogeneous Architecture Floorplan Optimization using
Analytical Methods},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {3:1--3:23},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857930},
doi = {10.1145/1857927.1857930},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KahoulSCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KanazawaM10,
author = {Kenji Kanazawa and
Tsutomu Maruyama},
title = {An Approach for Solving Large {SAT} Problems on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {10:1--10:21},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857937},
doi = {10.1145/1857927.1857937},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KanazawaM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KepaMKBHB10,
author = {Krzysztof Kepa and
Fearghal Morgan and
Krzysztof Kosciuszkiewicz and
Lars Braun and
Michael H{\"{u}}bner and
J{\"{u}}rgen Becker},
title = {Design Assurance Strategy and Toolset for Partially Reconfigurable
{FPGA} Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {4:1--4:26},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857931},
doi = {10.1145/1857927.1857931},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KepaMKBHB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KohD10,
author = {Shannon Koh and
Oliver Diessel},
title = {Configuration Merging in Point-to-Point Networks for Module-Based
{FPGA} Reconfiguration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {1},
pages = {4:1--4:36},
year = {2010},
url = {https://doi.org/10.1145/1661438.1661442},
doi = {10.1145/1661438.1661442},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KohD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LanuzzaZFPC10,
author = {Marco Lanuzza and
Paolo Zicari and
Fabio Frustaci and
Stefania Perri and
Pasquale Corsonello},
title = {Exploiting Self-Reconfiguration Capability to Improve SRAM-based {FPGA}
Robustness in Space and Avionics Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {8:1--8:22},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857935},
doi = {10.1145/1857927.1857935},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LanuzzaZFPC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LopesC10,
author = {Antonio Roldao Lopes and
George A. Constantinides},
title = {A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation
for Dense Matrices},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {1},
pages = {1:1--1:19},
year = {2010},
url = {https://doi.org/10.1145/1661438.1661439},
doi = {10.1145/1661438.1661439},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LopesC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuOM10,
author = {Yingxi Lu and
M{\'{a}}ire O'Neill and
John V. McCanny},
title = {Evaluation of Random Delay Insertion against {DPA} on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {11:1--11:20},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857938},
doi = {10.1145/1857927.1857938},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LuOM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MontoneSSM10,
author = {Alessio Montone and
Marco D. Santambrogio and
Donatella Sciuto and
Seda Ogrenci Memik},
title = {Placement and Floorplanning in Dynamically Reconfigurable FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {24:1--24:34},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862654},
doi = {10.1145/1862648.1862654},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MontoneSSM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MoscolaCC10,
author = {James Moscola and
Ron K. Cytron and
Young H. Cho},
title = {Hardware-Accelerated {RNA} Secondary-Structure Alignment},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {14:1--14:44},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839484},
doi = {10.1145/1839480.1839484},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MoscolaCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PapadopoulosP10,
author = {Konstantinos Papadopoulos and
Ioannis Papaefstathiou},
title = {Titan-R: {A} Multigigabit Reconfigurable Combined Compression/Decompression
Unit},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {2},
pages = {7:1--7:25},
year = {2010},
url = {https://doi.org/10.1145/1754386.1754388},
doi = {10.1145/1754386.1754388},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/PapadopoulosP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PurnaprajnaPRHTK10,
author = {Madhura Purnaprajna and
Mario Porrmann and
Ulrich R{\"{u}}ckert and
Michael Hussmann and
Michael Thies and
Uwe Kastens},
title = {Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {17:1--17:25},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839487},
doi = {10.1145/1839480.1839487},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PurnaprajnaPRHTK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ReardonGGW10,
author = {Casey Reardon and
Eric Grobelny and
Alan D. George and
Gongyu Wang},
title = {A Simulation Framework for Rapid Analysis of Reconfigurable Computing
Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {25:1--25:29},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862655},
doi = {10.1145/1862648.1862655},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ReardonGGW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SaiprasertBC10,
author = {Chalermpol Saiprasert and
Christos{-}Savvas Bouganis and
George A. Constantinides},
title = {An Optimized Hardware Architecture of a Multivariate Gaussian Random
Number Generator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {2:1--2:21},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857929},
doi = {10.1145/1857927.1857929},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SaiprasertBC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SaldanaPMNWCWSP10,
author = {Manuel Salda{\~{n}}a and
Arun Patel and
Christopher A. Madill and
Daniel Nunes and
Danyao Wang and
Paul Chow and
Ralph Wittig and
Henry Styles and
Andrew Putnam},
title = {{MPI} as a Programming Model for High-Performance Reconfigurable Computers},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {22:1--22:29},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862652},
doi = {10.1145/1862648.1862652},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SaldanaPMNWCWSP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SanoLHIY10,
author = {Kentaro Sano and
Luzhou Wang and
Yoshiaki Hatsuda and
Takanori Iizuka and
Satoru Yamamoto},
title = {FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient
Numerical Simulations Based on Finite Difference Methods},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {21:1--21:35},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862651},
doi = {10.1145/1862648.1862651},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SanoLHIY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SghaierAD10,
author = {Ahmad Sghaier and
Shawki Areibi and
Robert D. Dony},
title = {Implementation Approaches Trade-Offs for WiMax {OFDM} Functions on
Reconfigurable Platforms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {12:1--12:28},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839482},
doi = {10.1145/1839480.1839482},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SghaierAD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SmithCC10,
author = {Alastair M. Smith and
George A. Constantinides and
Peter Y. K. Cheung},
title = {An Automated Flow for Arithmetic Component Generation in Field-Programmable
Gate Arrays},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {13:1--13:21},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839483},
doi = {10.1145/1839480.1839483},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SmithCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Sterpone10,
author = {Luca Sterpone},
title = {A New Timing Driven Placement Algorithm for Dependable Circuits on
SRAM-based FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {7:1--7:21},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857934},
doi = {10.1145/1857927.1857934},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Sterpone10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TianB10,
author = {Xiang Tian and
Khaled Benkrid},
title = {High-Performance Quasi-Monte Carlo Financial Simulation: {FPGA} vs.
{GPP} vs. {GPU}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {26:1--26:22},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862656},
doi = {10.1145/1862648.1862656},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TianB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WangL10,
author = {Xiaojun Wang and
Miriam Leeser},
title = {VFloat: {A} Variable Precision Fixed- and Floating-Point Library for
Reconfigurable Hardware},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {3},
pages = {16:1--16:34},
year = {2010},
url = {https://doi.org/10.1145/1839480.1839486},
doi = {10.1145/1839480.1839486},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WangL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WilliamsMGRGL10,
author = {Jason Williams and
Chris Massie and
Alan D. George and
Justin Richardson and
Kunal Gosrani and
Herman Lam},
title = {Characterization of Fixed and Reconfigurable Multi-Core Devices for
Application Acceleration},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {4},
pages = {19:1--19:29},
year = {2010},
url = {https://doi.org/10.1145/1862648.1862649},
doi = {10.1145/1862648.1862649},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WilliamsMGRGL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WoodsBAM10,
author = {Roger F. Woods and
J{\"{u}}rgen Becker and
Peter Athanas and
Fearghal Morgan},
title = {Guest Editorial {ARC} 2009},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {1:1--1:2},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857928},
doi = {10.1145/1857927.1857928},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WoodsBAM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YooKBS10,
author = {Sang{-}Kyung Yoo and
Deniz Karakoyunlu and
Berk Birand and
Berk Sunar},
title = {Improving the Robustness of Ring Oscillator TRNGs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {3},
number = {2},
pages = {9:1--9:30},
year = {2010},
url = {https://doi.org/10.1145/1754386.1754390},
doi = {10.1145/1754386.1754390},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YooKBS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AhmedKA09,
author = {Taneem Ahmed and
Paul D. Kundarewich and
Jason Helge Anderson},
title = {Packing Techniques for Virtex-5 FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {3},
pages = {18:1--18:24},
year = {2009},
url = {https://doi.org/10.1145/1575774.1575777},
doi = {10.1145/1575774.1575777},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AhmedKA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AmanoN09,
author = {Hideharu Amano and
Tadao Nakamura},
title = {Guest Editors' Introduction: {ICFPT} 2007},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {7:1--7:2},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534917},
doi = {10.1145/1534916.1534917},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AmanoN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AngelopoulouBCC09,
author = {Maria E. Angelopoulou and
Christos{-}Savvas Bouganis and
Peter Y. K. Cheung and
George A. Constantinides},
title = {Robust Real-Time Super-Resolution on {FPGA} and an Application to
Video Enhancement},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {4},
pages = {22:1--22:29},
year = {2009},
url = {https://doi.org/10.1145/1575779.1575782},
doi = {10.1145/1575779.1575782},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AngelopoulouBCC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BouganisPCC09,
author = {Christos{-}Savvas Bouganis and
Sung{-}Boem Park and
George A. Constantinides and
Peter Y. K. Cheung},
title = {Synthesis and Optimization of 2D Filter Designs for Heterogeneous
FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {4},
pages = {24:1--24:28},
year = {2009},
url = {https://doi.org/10.1145/1462586.1462593},
doi = {10.1145/1462586.1462593},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BouganisPCC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CevreroAPVNNGBLI09,
author = {Alessandro Cevrero and
Panagiotis Athanasopoulos and
Hadi Parandeh{-}Afshar and
Ajay Kumar Verma and
Seyed{-}Hosein Attarzadeh{-}Niaki and
Chrysostomos Nicopoulos and
Frank K. G{\"{u}}rkaynak and
Philip Brisk and
Yusuf Leblebici and
Paolo Ienne},
title = {Field Programmable Compressor Trees: Acceleration of Multi-Input Addition
on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {13:1--13:36},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534923},
doi = {10.1145/1534916.1534923},
timestamp = {Tue, 03 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CevreroAPVNNGBLI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChinW09,
author = {Scott Y. L. Chin and
Steven J. E. Wilton},
title = {Static and Dynamic Memory Footprint Reduction for {FPGA} Routing Algorithms},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {4},
pages = {18:1--18:20},
year = {2009},
url = {https://doi.org/10.1145/1462586.1462587},
doi = {10.1145/1462586.1462587},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChinW09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChungPNHMF09,
author = {Eric S. Chung and
Michael Papamichael and
Eriko Nurvitadhi and
James C. Hoe and
Ken Mai and
Babak Falsafi},
title = {ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations
Using FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {15:1--15:32},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534925},
doi = {10.1145/1534916.1534925},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChungPNHMF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ComptonWBD09,
author = {Katherine Compton and
Roger F. Woods and
Christos{-}Savvas Bouganis and
Pedro C. Diniz},
title = {Introduction to the Special Issue ARC'08},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {4},
pages = {20:1},
year = {2009},
url = {https://doi.org/10.1145/1575779.1575780},
doi = {10.1145/1575779.1575780},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ComptonWBD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/CongZ09,
author = {Jason Cong and
Yi Zou},
title = {FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {3},
pages = {17:1--17:29},
year = {2009},
url = {https://doi.org/10.1145/1575774.1575776},
doi = {10.1145/1575774.1575776},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/CongZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DragomirSB09,
author = {Ozana Silvia Dragomir and
Todor P. Stefanov and
Koen Bertels},
title = {Optimal Loop Unrolling and Shifting for Reconfigurable Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {4},
pages = {25:1--25:24},
year = {2009},
url = {https://doi.org/10.1145/1575779.1575785},
doi = {10.1145/1575779.1575785},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DragomirSB09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DuttL09,
author = {Shantanu Dutt and
Li Li},
title = {Trust-Based Design and Check of {FPGA} Circuits Using Two-Level Randomized
{ECC} Structures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {1},
pages = {6:1--6:36},
year = {2009},
url = {https://doi.org/10.1145/1502781.1508209},
doi = {10.1145/1502781.1508209},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DuttL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/El-ArabyGE09,
author = {Esam El{-}Araby and
Iv{\'{a}}n Gonz{\'{a}}lez and
Tarek A. El{-}Ghazawi},
title = {Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable
Computing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {4},
pages = {21:1--21:23},
year = {2009},
url = {https://doi.org/10.1145/1462586.1462590},
doi = {10.1145/1462586.1462590},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/El-ArabyGE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HollandNG09,
author = {Brian Holland and
Karthik Nagarajan and
Alan D. George},
title = {{RAT:} {RC} Amenability Test for Rapid Performance Prediction},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {4},
pages = {22:1--22:31},
year = {2009},
url = {https://doi.org/10.1145/1462586.1462591},
doi = {10.1145/1462586.1462591},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HollandNG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JangCCM09,
author = {Stephen Jang and
Billy Chan and
Kevin Chung and
Alan Mishchenko},
title = {WireMap: {FPGA} Technology Mapping for Improved Routability and Enhanced
{LUT} Merging},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {14:1--14:24},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534924},
doi = {10.1145/1534916.1534924},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JangCCM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JinTLC09,
author = {Qiwei Jin and
David B. Thomas and
Wayne Luk and
Benjamin Cope},
title = {Exploring Reconfigurable Architectures for Tree-Based Option Pricing
Models},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {4},
pages = {21:1--21:17},
year = {2009},
url = {https://doi.org/10.1145/1575779.1575781},
doi = {10.1145/1575779.1575781},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/JinTLC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KellerBM09,
author = {Maurice Keller and
Andrew Byrne and
William P. Marnane},
title = {Elliptic Curve Cryptography on {FPGA} for Low-Power Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {1},
pages = {2:1--2:20},
year = {2009},
url = {https://doi.org/10.1145/1502781.1502783},
doi = {10.1145/1502781.1502783},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KellerBM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KochBT09,
author = {Dirk Koch and
Christian Beckhoff and
J{\"{u}}rgen Teich},
title = {Hardware Decompression Techniques for FPGA-Based Embedded Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {9:1--9:23},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534919},
doi = {10.1145/1534916.1534919},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KochBT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LoT09,
author = {Chia{-}Tien Dan Lo and
Yi{-}Gang Tai},
title = {Space Optimization on Counters for FPGA-Based Perl Compatible Regular
Expressions},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {4},
pages = {23:1--23:18},
year = {2009},
url = {https://doi.org/10.1145/1575779.1575783},
doi = {10.1145/1575779.1575783},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LoT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MajzoobiKP09,
author = {Mehrdad Majzoobi and
Farinaz Koushanfar and
Miodrag Potkonjak},
title = {Techniques for Design and Implementation of Secure Reconfigurable
PUFs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {1},
pages = {5:1--5:33},
year = {2009},
url = {https://doi.org/10.1145/1502781.1502786},
doi = {10.1145/1502781.1502786},
timestamp = {Fri, 04 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MajzoobiKP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/McEvoyMMT09,
author = {Robert P. McEvoy and
Colin C. Murphy and
William P. Marnane and
Michael Tunstall},
title = {Isolated {WDDL:} {A} Hiding Countermeasure for Differential Power
Analysis on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {1},
pages = {3:1--3:23},
year = {2009},
url = {https://doi.org/10.1145/1502781.1502784},
doi = {10.1145/1502781.1502784},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/McEvoyMMT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MurtazaHS09,
author = {S. Murtaza and
Alfons G. Hoekstra and
Peter M. A. Sloot},
title = {Compute Bound and {I/O} Bound Cellular Automata Simulations on {FPGA}
Logic},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {4},
pages = {23:1--23:21},
year = {2009},
url = {https://doi.org/10.1145/1462586.1462592},
doi = {10.1145/1462586.1462592},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MurtazaHS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Parandeh-AfsharBI09,
author = {Hadi Parandeh{-}Afshar and
Philip Brisk and
Paolo Ienne},
title = {An {FPGA} Logic Cell and Carry Chain Configurable as a 6: 2 or 7:
2 Compressor},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {3},
pages = {19:1--19:42},
year = {2009},
url = {https://doi.org/10.1145/1575774.1575778},
doi = {10.1145/1575774.1575778},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Parandeh-AfsharBI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PattersonEMDSKC09,
author = {Cameron D. Patterson and
Steven W. Ellingson and
Brian S. Martin and
K. Deshpande and
John H. Simonetti and
Michael Kavic and
Sean E. Cutchin},
title = {Searching for Transient Pulses with the {ETA} Radio Telescope},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {4},
pages = {20:1--20:19},
year = {2009},
url = {https://doi.org/10.1145/1462586.1462589},
doi = {10.1145/1462586.1462589},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PattersonEMDSKC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PellauerVAAE09,
author = {Michael Pellauer and
Muralidaran Vijayaraghavan and
Michael Adler and
Arvind and
Joel S. Emer},
title = {A-Port Networks: Preserving the Timed Behavior of Synchronous Systems
for Modeling on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {3},
pages = {16:1--16:26},
year = {2009},
url = {https://doi.org/10.1145/1575774.1575775},
doi = {10.1145/1575774.1575775},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PellauerVAAE09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SauvageGM09,
author = {Laurent Sauvage and
Sylvain Guilley and
Yves Mathieu},
title = {Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography
and Attack on a Cryptographic Module},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {1},
pages = {4:1--4:24},
year = {2009},
url = {https://doi.org/10.1145/1502781.1502785},
doi = {10.1145/1502781.1502785},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SauvageGM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SchaumontJT09,
author = {Patrick Schaumont and
Alex K. Jones and
Steve Trimberger},
title = {Guest Editors' Introduction to Security in Reconfigurable Systems
Design},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {1},
pages = {1:1--1:6},
year = {2009},
url = {https://doi.org/10.1145/1502781.1502782},
doi = {10.1145/1502781.1502782},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/SchaumontJT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SeetharamanV09,
author = {G. Seetharaman and
B. Venkataramani},
title = {Automation Schemes for {FPGA} Implementation of Wave-Pipelined Circuits},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {11:1--11:19},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534921},
doi = {10.1145/1534916.1534921},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SeetharamanV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/UnderwoodHU09,
author = {Keith D. Underwood and
K. Scott Hemmert and
Craig D. Ulmer},
title = {From Silicon to Science: The Long Road to Production Reconfigurable
Supercomputing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {4},
pages = {26:1--26:15},
year = {2009},
url = {https://doi.org/10.1145/1575779.1575786},
doi = {10.1145/1575779.1575786},
timestamp = {Sat, 28 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/UnderwoodHU09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/VassiliadisTN09,
author = {Nikolaos Vassiliadis and
George Theodoridis and
Spiridon Nikolaidis},
title = {An Application Development Framework for {ARISE} Reconfigurable Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {4},
pages = {24:1--24:30},
year = {2009},
url = {https://doi.org/10.1145/1575779.1575784},
doi = {10.1145/1575779.1575784},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/VassiliadisTN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WongSC09,
author = {Justin S. J. Wong and
N. Pete Sedcole and
Peter Y. K. Cheung},
title = {Self-Measurement of Combinatorial Circuit Delays in FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {10:1--10:22},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534920},
doi = {10.1145/1534916.1534920},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WongSC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/XuCGZH09,
author = {Ningyi Xu and
Xiongfei Cai and
Rui Gao and
Lei Zhang and
Feng{-}Hsiung Hsu},
title = {{FPGA} Acceleration of RankBoost in Web Search Engines},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {4},
pages = {19:1--19:19},
year = {2009},
url = {https://doi.org/10.1145/1462586.1462588},
doi = {10.1145/1462586.1462588},
timestamp = {Tue, 21 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/XuCGZH09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YuECPL09,
author = {Jason Yu and
Christopher Eagleston and
Christopher Han{-}Yu Chou and
Maxime Perreault and
Guy G. Lemieux},
title = {Vector Processing as a Soft Processor Accelerator},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {12:1--12:34},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534922},
doi = {10.1145/1534916.1534922},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/YuECPL09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhaoBCDP09,
author = {Weisheng Zhao and
Eric Belhaire and
Claude Chappert and
Bernard Dieny and
Guillaume Prenat},
title = {TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration {(RTR)}
{FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {2},
number = {2},
pages = {8:1--8:19},
year = {2009},
url = {https://doi.org/10.1145/1534916.1534918},
doi = {10.1145/1534916.1534918},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhaoBCDP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BeecklerG08,
author = {John Sachs Beeckler and
Warren J. Gross},
title = {Particle graphics on reconfigurable hardware},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {3},
pages = {15:1--15:27},
year = {2008},
url = {https://doi.org/10.1145/1391732.1391735},
doi = {10.1145/1391732.1391735},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BeecklerG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BuellL08,
author = {Duncan A. Buell and
Wayne Luk},
title = {Introduction},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {1},
pages = {1:1--1:2},
year = {2008},
url = {https://doi.org/10.1145/1331897.1331898},
doi = {10.1145/1331897.1331898},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/BuellL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DeHonH08,
author = {Andr{\'{e}} DeHon and
Mike Hutton},
title = {Guest Editorial: {TRETS} Special Edition on the 15th International
Symposium on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {1},
pages = {2:1--2:3},
year = {2008},
url = {https://doi.org/10.1145/1331897.1341292},
doi = {10.1145/1331897.1341292},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DeHonH08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/FengK08,
author = {Wenyi Feng and
Sinan Kaptanoglu},
title = {Designing Efficient Input Interconnect Blocks for {LUT} Clusters Using
Counting and Entropy},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {1},
pages = {6:1--6:28},
year = {2008},
url = {https://doi.org/10.1145/1331897.1331902},
doi = {10.1145/1331897.1331902},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/FengK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GorjiaraRG08,
author = {Bita Gorjiara and
Mehrdad Reshadi and
Daniel Gajski},
title = {Merged Dictionary Code Compression for {FPGA} Implementation of Custom
Microcoded PEs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {2},
pages = {11:1--11:21},
year = {2008},
url = {https://doi.org/10.1145/1371579.1371583},
doi = {10.1145/1371579.1371583},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GorjiaraRG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GrantL08,
author = {David Grant and
Guy G. Lemieux},
title = {Perturb+mutate: Semisynthetic circuit generation for incremental placement
and routing},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {3},
pages = {16:1--16:24},
year = {2008},
url = {https://doi.org/10.1145/1391732.1391736},
doi = {10.1145/1391732.1391736},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GrantL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GuneysuPP08,
author = {Tim G{\"{u}}neysu and
Christof Paar and
Jan Pelzl},
title = {Special-Purpose Hardware for Solving the Elliptic Curve Discrete Logarithm
Problem},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {2},
pages = {8:1--8:21},
year = {2008},
url = {https://doi.org/10.1145/1371579.1371580},
doi = {10.1145/1371579.1371580},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GuneysuPP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/HsiungLL08,
author = {Pao{-}Ann Hsiung and
Chao{-}Sheng Lin and
Chih{-}Feng Liao},
title = {Perfecto: {A} systemc-based design-space exploration framework for
dynamically reconfigurable architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {3},
pages = {17:1--17:30},
year = {2008},
url = {https://doi.org/10.1145/1391732.1391737},
doi = {10.1145/1391732.1391737},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/HsiungLL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/JacobLBHC08,
author = {Arpith C. Jacob and
Joseph M. Lancaster and
Jeremy Buhler and
Brandon Harris and
Roger D. Chamberlain},
title = {Mercury {BLASTP:} Accelerating Protein Sequence Alignment},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {2},
pages = {9:1--9:44},
year = {2008},
url = {https://doi.org/10.1145/1371579.1371581},
doi = {10.1145/1371579.1371581},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/JacobLBHC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LamoureuxW08,
author = {Julien Lamoureux and
Steven J. E. Wilton},
title = {On the trade-off between power and flexibility of {FPGA} clock networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {3},
pages = {13:1--13:33},
year = {2008},
url = {https://doi.org/10.1145/1391732.1391733},
doi = {10.1145/1391732.1391733},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LamoureuxW08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuYSKK08,
author = {Shih{-}Lien Lu and
Peter Yiannacouras and
Taeweon Suh and
Rolf Kassa and
Michael Konow},
title = {A Desktop Computer with a Reconfigurable Pentium{\textregistered}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {1},
pages = {5:1--5:15},
year = {2008},
url = {https://doi.org/10.1145/1331897.1331901},
doi = {10.1145/1331897.1331901},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/LuYSKK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MatsumotoHKKTNS08,
author = {Yohei Matsumoto and
Masakazu Hioki and
Takashi Kawanami and
Hanpei Koike and
Toshiyuki Tsutsumi and
Tadashi Nakagawa and
Toshihiro Sekigawa},
title = {Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {1},
pages = {3:1--3:31},
year = {2008},
url = {https://doi.org/10.1145/1331897.1331899},
doi = {10.1145/1331897.1331899},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/MatsumotoHKKTNS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SedcoleC08,
author = {N. Pete Sedcole and
Peter Y. K. Cheung},
title = {Parametric Yield Modeling and Simulations of {FPGA} Circuits Considering
Within-Die Delay Variations},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {2},
pages = {10:1--10:28},
year = {2008},
url = {https://doi.org/10.1145/1371579.1371582},
doi = {10.1145/1371579.1371582},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SedcoleC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SivaswamyB08,
author = {Satish Sivaswamy and
Kia Bazargan},
title = {Statistical Analysis and Process Variation-Aware Routing and Skew
Assignment for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {1},
pages = {4:1--4:35},
year = {2008},
url = {https://doi.org/10.1145/1331897.1331900},
doi = {10.1145/1331897.1331900},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SivaswamyB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/SlogsnatGNB08,
author = {David Slogsnat and
Alexander Giese and
Mondrian N{\"{u}}ssle and
Ulrich Br{\"{u}}ning},
title = {An open-source HyperTransport core},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {3},
pages = {14:1--14:21},
year = {2008},
url = {https://doi.org/10.1145/1391732.1391734},
doi = {10.1145/1391732.1391734},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/SlogsnatGNB08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ThomasL08,
author = {David B. Thomas and
Wayne Luk},
title = {Multivariate Gaussian Random Number Generation Targeting Reconfigurable
Hardware},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {2},
pages = {12:1--12:29},
year = {2008},
url = {https://doi.org/10.1145/1371579.1371584},
doi = {10.1145/1371579.1371584},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ThomasL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WiltonHQLL08,
author = {Steven J. E. Wilton and
Chun Hok Ho and
Bradley R. Quinton and
Philip Heng Wai Leong and
Wayne Luk},
title = {A Synthesizable Datapath-Oriented Embedded {FPGA} Fabric for Silicon
Debug Applications},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {1},
number = {1},
pages = {7:1--7:25},
year = {2008},
url = {https://doi.org/10.1145/1331897.1331903},
doi = {10.1145/1331897.1331903},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WiltonHQLL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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