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@article{DBLP:journals/ipsj/IizukaIYA24,
author = {Kensuke Iizuka and
Kohei Ito and
Ryota Yasudo and
Hideharu Amano},
title = {Power Optimized Design Framework for {FPGA} Clusters},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {77--86},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.77},
doi = {10.2197/IPSJTSLDM.17.77},
timestamp = {Thu, 08 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/IizukaIYA24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Ishihara24,
author = {Tohru Ishihara},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {1},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.1},
doi = {10.2197/IPSJTSLDM.17.1},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/Ishihara24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KitamuraHWI24,
author = {Takehiro Kitamura and
Takashi Hisakado and
Osami Wada and
Mahfuzul Islam},
title = {Design of Reference-free Flash {ADC} With On-chip Rank-based Comparator
Selection Using Multiple Comparator Groups},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {36--43},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.36},
doi = {10.2197/IPSJTSLDM.17.36},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/KitamuraHWI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Kuroda24,
author = {Tadahiro Kuroda},
title = {Slashing {IC} Power and Democratizing {IC} Access for the Digital
Age},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {2--6},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.2},
doi = {10.2197/IPSJTSLDM.17.2},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/Kuroda24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NakabeppuY24,
author = {Shota Nakabeppu and
Nobuyuki Yamasaki},
title = {A Learning-based Control Scheme for MTJ-based Non-volatile Flip-Flops},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {16--35},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.16},
doi = {10.2197/IPSJTSLDM.17.16},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/NakabeppuY24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/OharaFTKHIIK24,
author = {Ryotaro Ohara and
Atsushi Fukunaga and
Masakazu Taichi and
Masaya Kabuto and
Riku Hamabe and
Masato Ikegawa and
Shintaro Izumi and
Hiroshi Kawaguchi},
title = {A Case Study for Improving Performances of Deep-Learning Processor
with {MRAM}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {7--15},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.7},
doi = {10.2197/IPSJTSLDM.17.7},
timestamp = {Tue, 19 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/OharaFTKHIIK24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TaniguchiTTMMN24,
author = {Kazuya Taniguchi and
Satoshi Tayu and
Atsushi Takahashi and
Mathieu Molongo and
Makoto Minami and
Katsuya Nishioka},
title = {Two-layer Bottleneck Channel Track Assignment for Analog {VLSI}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {67--76},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.67},
doi = {10.2197/IPSJTSLDM.17.67},
timestamp = {Thu, 08 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TaniguchiTTMMN24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/WangLI24,
author = {Hansen Wang and
Dongju Li and
Tsuyoshi Isshiki},
title = {A Low-Power Reconfigurable {DNN} Accelerator for Instruction-Extended
{RISC-V}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {55--66},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.55},
doi = {10.2197/IPSJTSLDM.17.55},
timestamp = {Thu, 08 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/WangLI24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhangO24,
author = {Yuncheng Zhang and
Kenichi Okada},
title = {Design of Synthesizable Digital Phase Locked Loops},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {17},
pages = {44--54},
year = {2024},
url = {https://doi.org/10.2197/ipsjtsldm.17.44},
doi = {10.2197/IPSJTSLDM.17.44},
timestamp = {Thu, 08 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhangO24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Hamaguchi23,
author = {Kiyoharu Hamaguchi},
title = {Parallelizing Random and SAT-based Verification Processes for Improving
Toggle Coverage},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {16},
pages = {45--53},
year = {2023},
url = {https://doi.org/10.2197/ipsjtsldm.16.45},
doi = {10.2197/IPSJTSLDM.16.45},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Hamaguchi23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KataokaYINW23,
author = {Gaku Kataoka and
Masahiro Yamamoto and
Masato Inagi and
Shinobu Nagayama and
Shin'ichi Wakabayashi},
title = {Feature Vectors Based on Wire Width and Distance for Lithography Hotspot
Detection},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {16},
pages = {2--11},
year = {2023},
url = {https://doi.org/10.2197/ipsjtsldm.16.2},
doi = {10.2197/IPSJTSLDM.16.2},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/KataokaYINW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SadasueI23,
author = {Tamon Sadasue and
Tsuyoshi Isshiki},
title = {{LLVM-C2RTL:} {C/C++} Based System Level {RTL} Design Framework Using
{LLVM} Compiler Infrastructure},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {16},
pages = {12--26},
year = {2023},
url = {https://doi.org/10.2197/ipsjtsldm.16.12},
doi = {10.2197/IPSJTSLDM.16.12},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SadasueI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShimamuraTI23,
author = {Kotaro Shimamura and
Takeshi Takehara and
Naohiro Ikeda},
title = {Measurement Results of Real Circuit Delay Degradation under Realistic
Workload},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {16},
pages = {27--34},
year = {2023},
url = {https://doi.org/10.2197/ipsjtsldm.16.27},
doi = {10.2197/IPSJTSLDM.16.27},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/ShimamuraTI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Takahashi23,
author = {Atsushi Takahashi},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {16},
pages = {1},
year = {2023},
url = {https://doi.org/10.2197/ipsjtsldm.16.1},
doi = {10.2197/IPSJTSLDM.16.1},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Takahashi23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TanakaMKIO23,
author = {Ippei Tanaka and
Naoyuki Miyagawa and
Tomoya Kimura and
Takashi Imagawa and
Hiroyuki Ochi},
title = {A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage
Capacitor},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {16},
pages = {35--44},
year = {2023},
url = {https://doi.org/10.2197/ipsjtsldm.16.35},
doi = {10.2197/IPSJTSLDM.16.35},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/TanakaMKIO23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NakaharaMKAI22,
author = {Yasuhiro Nakahara and
Yuta Masuda and
Masato Kiyama and
Motoki Amagasaki and
Masahiro Iida},
title = {A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep
Neural Networks},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {15},
pages = {16--19},
year = {2022},
url = {https://doi.org/10.2197/ipsjtsldm.15.16},
doi = {10.2197/IPSJTSLDM.15.16},
timestamp = {Fri, 24 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NakaharaMKAI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Takahashi22,
author = {Atsushi Takahashi},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {15},
pages = {1},
year = {2022},
url = {https://doi.org/10.2197/ipsjtsldm.15.1},
doi = {10.2197/IPSJTSLDM.15.1},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Takahashi22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YuMF22,
author = {Mingfei Yu and
Yukio Miyasaka and
Masahiro Fujita},
title = {Parallel Scheduling Attention Mechanism: Generalization and Optimization},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {15},
pages = {2--15},
year = {2022},
url = {https://doi.org/10.2197/ipsjtsldm.15.2},
doi = {10.2197/IPSJTSLDM.15.2},
timestamp = {Fri, 24 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YuMF22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ItoNKFSNTT21,
author = {Satoshi Ito and
Hiroki Nishikawa and
Xiangbo Kong and
Yusuke Funabashi and
Atsuya Shibata and
Shunsuke Negoro and
Ittetsu Taniguchi and
Hiroyuki Tomiyama},
title = {Energy-aware Routing of Delivery Drones under Windy Conditions},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {30--39},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.30},
doi = {10.2197/IPSJTSLDM.14.30},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ItoNKFSNTT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MukasaTT21,
author = {Yosuke Mukasa and
Shu Tanaka and
Nozomu Togawa},
title = {Experimental Evaluations of Parallel Tempering on an Ising Machine},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {27--29},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.27},
doi = {10.2197/IPSJTSLDM.14.27},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MukasaTT21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NishizawaLLO21,
author = {Shinichi Nishizawa and
Shih{-}Ting Lin and
Yih{-}Lang Li and
Hidetoshi Onodera},
title = {Supplemental {PDK} for {ASAP7} Using Synopsys Flow},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {24--26},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.24},
doi = {10.2197/IPSJTSLDM.14.24},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NishizawaLLO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SadasueTKDI21,
author = {Tamon Sadasue and
Takuya Tanaka and
Ryosuke Kasahara and
Arief Darmawan and
Tsuyoshi Isshiki},
title = {Scalable Hardware Architecture for fast Gradient Boosted Tree Training},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {11--20},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.11},
doi = {10.2197/IPSJTSLDM.14.11},
timestamp = {Fri, 16 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SadasueTKDI21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Shin21,
author = {Youngsoo Shin},
title = {Computational Lithography Using Machine Learning Models},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {2--10},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.2},
doi = {10.2197/IPSJTSLDM.14.2},
timestamp = {Fri, 16 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Shin21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Takahashi21,
author = {Atsushi Takahashi},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {1},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.1},
doi = {10.2197/IPSJTSLDM.14.1},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Takahashi21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhaoTO21,
author = {Qiaochu Zhao and
Ittetsu Taniguchi and
Takao Onoye},
title = {A Case Study on {FPGA} Implementation of Parts Counting Orientation
Recognition Method for Industrial Vision System},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {14},
pages = {21--23},
year = {2021},
url = {https://doi.org/10.2197/ipsjtsldm.14.21},
doi = {10.2197/IPSJTSLDM.14.21},
timestamp = {Fri, 16 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhaoTO21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AmagasakiOFIYI20,
author = {Motoki Amagasaki and
Hiroki Oyama and
Yuichiro Fujishiro and
Masahiro Iida and
Hiroaki Yasuda and
Hiroto Ito},
title = {{R-GCN} Based Function Inference for Gate-level Netlist},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {69--71},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.69},
doi = {10.2197/IPSJTSLDM.13.69},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AmagasakiOFIYI20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/FunabashiSNTT20,
author = {Yusuke Funabashi and
Atsuya Shibata and
Shunsuke Negoro and
Ittetsu Taniguchi and
Hiroyuki Tomiyama},
title = {A Dynamic Programming Algorithm for Energy-aware Routing of Delivery
Drones},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {65--68},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.65},
doi = {10.2197/IPSJTSLDM.13.65},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/FunabashiSNTT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HosakaNKMK20,
author = {Takumi Hosaka and
Shinichi Nishizawa and
Ryo Kishida and
Takashi Matsumoto and
Kazutoshi Kobayashi},
title = {Universal {NBTI} Compact Model Replicating {AC} Stress/Recovery from
a Single-shot Long-term {DC} Measurement},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {56--64},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.56},
doi = {10.2197/IPSJTSLDM.13.56},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HosakaNKMK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/IshikawaTYT20,
author = {Ryota Ishikawa and
Masashi Tawada and
Masao Yanagisawa and
Nozomu Togawa},
title = {Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic
Circuit Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {10--20},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.10},
doi = {10.2197/IPSJTSLDM.13.10},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/IshikawaTYT20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MitsuyamaAE20,
author = {Yukio Mitsuyama and
Takashi Asada and
Makio Eguchi},
title = {Measurement of Variations in FPGAs under Various Load Conditions},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {39--41},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.39},
doi = {10.2197/IPSJTSLDM.13.39},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MitsuyamaAE20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MiyasakaGMF20,
author = {Yukio Miyasaka and
Akihiro Goda and
Ashish Mittal and
Masahiro Fujita},
title = {Synthesis and Generalization of Parallel Algorithm for Matrix-vector
Multiplication},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {31--34},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.31},
doi = {10.2197/IPSJTSLDM.13.31},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MiyasakaGMF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Seto20,
author = {Kenshu Seto},
title = {Shift Register Initialization in Scalar Replacement for Reducing Code
Size},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {2--9},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.2},
doi = {10.2197/IPSJTSLDM.13.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Seto20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShimamuraI20,
author = {Kotaro Shimamura and
Naohiro Ikeda},
title = {Real Circuit Delay Measurement Method by Variable Frequency Operation
with On-Chip Fine Resolution Oscillator},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {21--30},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.21},
doi = {10.2197/IPSJTSLDM.13.21},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShimamuraI20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Takahashi20,
author = {Atsushi Takahashi},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {1},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.1},
doi = {10.2197/IPSJTSLDM.13.1},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Takahashi20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TanSS20,
author = {Sheldon X.{-}D. Tan and
Zeyu Sun and
Sheriff Sadiqbatcha},
title = {Interconnect Electromigration Modeling and Analysis for Nanometer
ICs: From Physics to Full-Chip},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {42--55},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.42},
doi = {10.2197/IPSJTSLDM.13.42},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/TanSS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/WangGF20,
author = {Peikun Wang and
Amir Masoud Gharehbaghi and
Masahiro Fujita},
title = {A Logic Optimization Method by Eliminating Redundant Multiple Faults
from Higher to Lower Cardinality},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {35--38},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.35},
doi = {10.2197/IPSJTSLDM.13.35},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/WangGF20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/FujiwaraKYT19,
author = {Koichi Fujiwara and
Kazushi Kawamura and
Masao Yanagisawa and
Nozomu Togawa},
title = {An {FPGA} Implementation Method based on Distributed-register Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {38--41},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.38},
doi = {10.2197/IPSJTSLDM.12.38},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/FujiwaraKYT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/IslamO19,
author = {A. K. M. Mahfuzul Islam and
Hidetoshi Onodera},
title = {Circuit Techniques for Device-Circuit Interaction toward Minimum Energy
Operation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {2--12},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.2},
doi = {10.2197/IPSJTSLDM.12.2},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/IslamO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KitoTT19,
author = {Nobutaka Kito and
Kazuyoshi Takagi and
Naofumi Takagi},
title = {Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum
Circuits Utilizing Confluence of Pulses},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {78--80},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.78},
doi = {10.2197/IPSJTSLDM.12.78},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/KitoTT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KoyasuT19,
author = {Hiroki Koyasu and
Yasuhiro Takahashi},
title = {Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic
Circuits},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {50--52},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.50},
doi = {10.2197/IPSJTSLDM.12.50},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KoyasuT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/LiuMT19,
author = {Yang Liu and
Lin Meng and
Hiroyuki Tomiyama},
title = {A Genetic Algorithm for Scheduling of Data-parallel Tasks on Multicore
Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {74--77},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.74},
doi = {10.2197/IPSJTSLDM.12.74},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/LiuMT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MiyazakiTTT19,
author = {Takafumi Miyazaki and
Shunsuke Takai and
Ittetsu Taniguchi and
Hiroyuki Tomiyama},
title = {An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture
on Zynq-7000 SoC},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {46--49},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.46},
doi = {10.2197/IPSJTSLDM.12.46},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/MiyazakiTTT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Seto19,
author = {Kenshu Seto},
title = {Scalar Replacement with Circular Buffers},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {13--21},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.13},
doi = {10.2197/IPSJTSLDM.12.13},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Seto19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShimadaTT19,
author = {Kana Shimada and
Ittetsu Taniguchi and
Hiroyuki Tomiyama},
title = {Communication-Aware Scheduling of Data-Parallel Tasks on Multicore
Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {65--73},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.65},
doi = {10.2197/IPSJTSLDM.12.65},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShimadaTT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShirakuniTT19,
author = {Seiya Shirakuni and
Ittetsu Taniguchi and
Hiroyuki Tomiyama},
title = {Design and Evaluation of Asymmetric and Symmetric 32-core Architectures
on {FPGA}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {42--45},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.42},
doi = {10.2197/IPSJTSLDM.12.42},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/ShirakuniTT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SombatsiriSKITH19,
author = {Salita Sombatsiri and
Seiya Shibata and
Yuki Kobayashi and
Hiroaki Inoue and
Takashi Takenaka and
Takeo Hosomi and
Jaehoon Yu and
Yoshinori Takeuchi},
title = {Parallelism-flexible Convolution Core for Sparse Convolutional Neural
Networks on {FPGA}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {22--37},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.22},
doi = {10.2197/IPSJTSLDM.12.22},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SombatsiriSKITH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Togawa19,
author = {Nozomu Togawa},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {1},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.1},
doi = {10.2197/IPSJTSLDM.12.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Togawa19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YangQC19,
author = {Chaofei Yang and
Ximing Qiao and
Yiran Chen},
title = {Neuromorphic Computing Systems: From {CMOS} To Emerging Nonvolatile
Memory},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {12},
pages = {53--64},
year = {2019},
url = {https://doi.org/10.2197/ipsjtsldm.12.53},
doi = {10.2197/IPSJTSLDM.12.53},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YangQC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/DiepenbeckKSGD18,
author = {Melanie Diepenbeck and
Ulrich K{\"{u}}hne and
Mathias Soeken and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Behaviour Driven Development for Hardware Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {11},
pages = {29--45},
year = {2018},
url = {https://doi.org/10.2197/ipsjtsldm.11.29},
doi = {10.2197/IPSJTSLDM.11.29},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/DiepenbeckKSGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/LiHS18,
author = {Bing Li and
Masanori Hashimoto and
Ulf Schlichtmann},
title = {From Process Variations to Reliability: {A} Survey of Timing of Digital
Circuits in the Nanometer Era},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {11},
year = {2018},
url = {https://doi.org/10.2197/ipsjtsldm.11.2},
doi = {10.2197/IPSJTSLDM.11.2},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/LiHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/OkuYT18,
author = {Daisuke Oku and
Masao Yanagisawa and
Nozomu Togawa},
title = {Scan-based Side-channel Attack against {HMAC-SHA-256} Circuits Based
on Isolating Bit-transition Groups Using Scan Signatures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {11},
year = {2018},
url = {https://doi.org/10.2197/ipsjtsldm.11.16},
doi = {10.2197/IPSJTSLDM.11.16},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/OkuYT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Seto18,
author = {Kenshu Seto},
title = {Scalar Replacement with Polyhedral Model},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {11},
pages = {46--56},
year = {2018},
url = {https://doi.org/10.2197/ipsjtsldm.11.46},
doi = {10.2197/IPSJTSLDM.11.46},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Seto18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Togawa18,
author = {Nozomu Togawa},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {11},
year = {2018},
url = {https://doi.org/10.2197/ipsjtsldm.11.1},
doi = {10.2197/IPSJTSLDM.11.1},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/Togawa18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AwadTTK17,
author = {Ahmed Awad and
Atsushi Takahashi and
Satoshi Tanaka and
Chikaaki Kodama},
title = {Intensity Difference Map {(IDM)} Accuracy Analysis for {OPC} Efficiency
Verification and Further Enhancement},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {28--38},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.28},
doi = {10.2197/IPSJTSLDM.10.28},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AwadTTK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KnechtelSELS17,
author = {Johann Knechtel and
Ozgur Sinanoglu and
Ibrahim Abe M. Elfadel and
Jens Lienig and
Cliff C. N. Sze},
title = {Large-Scale 3D Chips: Challenges and Solutions for Design Automation,
Testing, and Trustworthy Integration},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {45--62},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.45},
doi = {10.2197/IPSJTSLDM.10.45},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/KnechtelSELS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Matsunaga17,
author = {Yusuke Matsunaga},
title = {An Accelerating Technique for SAT-based {ATPG}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {39--44},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.39},
doi = {10.2197/IPSJTSLDM.10.39},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Matsunaga17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShafiqIL17,
author = {Farhan Shafiq and
Tsuyoshi Isshiki and
Dongju Li},
title = {An Accurate and Fast Trace-aware Performance Estimation Model For
Prioritized MPSoC Bus With Multiple Interfering Bus-Masters},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {13--27},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.13},
doi = {10.2197/IPSJTSLDM.10.13},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShafiqIL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Togawa17,
author = {Nozomu Togawa},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {1},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.1},
doi = {10.2197/IPSJTSLDM.10.1},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/Togawa17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/XuP17,
author = {Xiaoqing Xu and
David Z. Pan},
title = {Toward Unidirectional Routing Closure in Advanced Technology Nodes},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {2--12},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.2},
doi = {10.2197/IPSJTSLDM.10.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/XuP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhaoAIKS17,
author = {Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Towards Open-HW: {A} Platform to Design, Share and Deploy {FPGA} Accelerators
in Low Cost},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {63--70},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.63},
doi = {10.2197/IPSJTSLDM.10.63},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhaoAIKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AwadBWS16,
author = {Amro Awad and
Ganesh Balakrishnan and
Yipeng Wang and
Yan Solihin},
title = {Accurate Cloning of the Memory Access Behavior},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {49--60},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.49},
doi = {10.2197/IPSJTSLDM.9.49},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AwadBWS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ChowY16,
author = {Wing{-}Kai Chow and
Evangeline F. Y. Young},
title = {Placement: From Wirelength to Detailed Routability},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {2--12},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.2},
doi = {10.2197/IPSJTSLDM.9.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ChowY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/CuiN16,
author = {Ri Cui and
Kazuteru Namba},
title = {A Calibration Technique for {DVMC} with Delay Time Controllable Inverter},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {30--36},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.30},
doi = {10.2197/IPSJTSLDM.9.30},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/CuiN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HashimotoI16,
author = {Atsushi Hashimoto and
Nagisa Ishiura},
title = {Detecting Arithmetic Optimization Opportunities for {C} Compilers
by Randomly Generated Equivalent Programs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {21--29},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.21},
doi = {10.2197/IPSJTSLDM.9.21},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HashimotoI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HigamiWTKS16,
author = {Yoshinobu Higami and
Senling Wang and
Hiroshi Takahashi and
Shin{-}ya Kobayashi and
Kewal K. Saluja},
title = {Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {13--20},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.13},
doi = {10.2197/IPSJTSLDM.9.13},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HigamiWTKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShafiqILK16,
author = {Farhan Shafiq and
Tsuyoshi Isshiki and
Dongju Li and
Hiroaki Kunieda},
title = {A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic
Modeling for Contention Stall in {A} Priority Based MPSoC Bus},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {37--48},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.37},
doi = {10.2197/IPSJTSLDM.9.37},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShafiqILK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SutisnaHLNKO16,
author = {Nana Sutisna and
Reina Hongyo and
Leonardo Lanante and
Yuhei Nagao and
Masayuki Kurosaki and
Hiroshi Ochi},
title = {Unified {HW/SW} Co-Verification Methodology for High Throughput Wireless
Communication System},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {61--71},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.61},
doi = {10.2197/IPSJTSLDM.9.61},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/SutisnaHLNKO16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Togawa16,
author = {Nozomu Togawa},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {1},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.1},
doi = {10.2197/IPSJTSLDM.9.1},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/Togawa16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/UmekiYYIYKTS16,
author = {Yohei Umeki and
Koji Yanagida and
Shusuke Yoshimoto and
Shintaro Izumi and
Masahiko Yoshimoto and
Hiroshi Kawaguchi and
Koji Tsunoda and
Toshihiro Sugii},
title = {A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V
Operating {STT-MRAM}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {79--83},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.79},
doi = {10.2197/IPSJTSLDM.9.79},
timestamp = {Mon, 11 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/UmekiYYIYKTS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YabuuchiK16,
author = {Michitarou Yabuuchi and
Kazutoshi Kobayashi},
title = {Size Optimization Technique for Logic Circuits that Considers {BTI}
and Process Variations},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {9},
pages = {72--78},
year = {2016},
url = {https://doi.org/10.2197/ipsjtsldm.9.72},
doi = {10.2197/IPSJTSLDM.9.72},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YabuuchiK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/0001WW15,
author = {Matthias Jung and
Christian Weis and
Norbert Wehn},
title = {DRAMSys: {A} Flexible {DRAM} Subsystem Design Space Exploration Framework},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {63--74},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.63},
doi = {10.2197/IPSJTSLDM.8.63},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/0001WW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AmagasakiZIKS15,
author = {Motoki Amagasaki and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {A 3D {FPGA} Architecture to Realize Simple Die Stacking},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {116--122},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.116},
doi = {10.2197/IPSJTSLDM.8.116},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AmagasakiZIKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AndoIHTE15,
author = {Yuki Ando and
Yukihito Ishida and
Shinya Honda and
Hiroaki Takada and
Masato Edahiro},
title = {Automatic Synthesis of Inter-heterogeneous-processor Communication
for Programmable System-on-chip},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {95--99},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.95},
doi = {10.2197/IPSJTSLDM.8.95},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AndoIHTE15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HatayamaTTT15,
author = {Takuya Hatayama and
Hideki Takase and
Kazuyoshi Takagi and
Naofumi Takagi},
title = {An Allocation Optimization Method for Partially-reliable Scratch-pad
Memory in Embedded Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {100--104},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.100},
doi = {10.2197/IPSJTSLDM.8.100},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/HatayamaTTT15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HiraiYM15,
author = {Yusaku Hirai and
Shinya Yano and
Toshimasa Matsuoka},
title = {A Delta-Sigma {ADC} with Stochastic Quantization},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {123--130},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.123},
doi = {10.2197/IPSJTSLDM.8.123},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HiraiYM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KhanILK15,
author = {Arif Ullah Khan and
Tsuyoshi Isshiki and
Dongju Li and
Hiroaki Kunieda},
title = {Efficient Design Exploration Framework of {SW/HW} Systems Based on
Tightly-coupled Thread Model},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {38--50},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.38},
doi = {10.2197/IPSJTSLDM.8.38},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KhanILK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Mitra15,
author = {Tulika Mitra},
title = {Heterogeneous Multi-core Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {51--62},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.51},
doi = {10.2197/IPSJTSLDM.8.51},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Mitra15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MiyajimaTA15,
author = {Takaaki Miyajima and
David B. Thomas and
Hideharu Amano},
title = {Courier: {A} Toolchain for Application Acceleration on Heterogeneous
Platforms},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {105--115},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.105},
doi = {10.2197/IPSJTSLDM.8.105},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MiyajimaTA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NishizawaIO15,
author = {Shinichi Nishizawa and
Tohru Ishihara and
Hidetoshi Onodera},
title = {Layout Generator with Flexible Grid Assignment for Area Efficient
Standard Cell},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {131--135},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.131},
doi = {10.2197/IPSJTSLDM.8.131},
timestamp = {Sun, 04 Aug 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NishizawaIO15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SombatsiriTI15,
author = {Salita Sombatsiri and
Yoshinori Takeuchi and
Masaharu Imai},
title = {An Efficient Performance Estimation Method for Configurable Multi-layer
Bus-based SoC},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {26--37},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.26},
doi = {10.2197/IPSJTSLDM.8.26},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SombatsiriTI15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Tomiyama15,
author = {Hiroyuki Tomiyama},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {1},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.1},
doi = {10.2197/IPSJTSLDM.8.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Tomiyama15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZengJW15,
author = {Lian Zeng and
Xin Jiang and
Takahiro Watanabe},
title = {A Performance Enhanced Dual-switch Network-on-chip Architecture},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {85--94},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.85},
doi = {10.2197/IPSJTSLDM.8.85},
timestamp = {Tue, 26 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZengJW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhangCDC15,
author = {Zhiru Zhang and
Deming Chen and
Steve Dai and
Keith A. Campbell},
title = {High-level Synthesis for Low-power Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {12--25},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.12},
doi = {10.2197/IPSJTSLDM.8.12},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/ZhangCDC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhangPZW15,
author = {Ran Zhang and
Tieyuan Pan and
Li Zhu and
Takahiro Watanabe},
title = {Layer Assignment and Equal-length Routing for Disordered Pins in {PCB}
Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {75--84},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.75},
doi = {10.2197/IPSJTSLDM.8.75},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhangPZW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhaoXC015,
author = {Jishen Zhao and
Cong Xu and
Ping Chi and
Yuan Xie},
title = {Memory and Storage System Design with Nonvolatile Memory Technologies},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {2--11},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.2},
doi = {10.2197/IPSJTSLDM.8.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhaoXC015.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AkasakaAYT14,
author = {Hiroyuki Akasaka and
Shin{-}ya Abe and
Masao Yanagisawa and
Nozomu Togawa},
title = {Energy-efficient High-level Synthesis for {HDR} Architecture with
Multi-stage Clock Gating},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {74--80},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.74},
doi = {10.2197/IPSJTSLDM.7.74},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/AkasakaAYT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ChakrabartyADNWY14,
author = {Krishnendu Chakrabarty and
Mukesh Agrawal and
Sergej Deutsch and
Brandon Noia and
Ran Wang and
Fangming Ye},
title = {Test and Design-for-Testability Solutions for 3D Integrated Circuits},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {56--73},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.56},
doi = {10.2197/IPSJTSLDM.7.56},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/ChakrabartyADNWY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HagioYT14,
author = {Yuta Hagio and
Masao Yanagisawa and
Nozomu Togawa},
title = {A Delay-variation-aware High-level Synthesis Algorithm for {RDR} Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {81--90},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.81},
doi = {10.2197/IPSJTSLDM.7.81},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/HagioYT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Hara-AzumiMTHT14,
author = {Yuko Hara{-}Azumi and
Toshinobu Matsuba and
Hiroyuki Tomiyama and
Shinya Honda and
Hiroaki Takada},
title = {Impact of Resource Sharing and Register Retiming on Area and Performance
of FPGA-based Designs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {37--45},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.37},
doi = {10.2197/IPSJTSLDM.7.37},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Hara-AzumiMTHT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Ho14,
author = {Tsung{-}Yi Ho},
title = {Design Automation for Digital Microfluidic Biochips},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {16--26},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.16},
doi = {10.2197/IPSJTSLDM.7.16},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Ho14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/JiangZW14,
author = {Xin Jiang and
Lian Zeng and
Takahiro Watanabe},
title = {A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low
Energy and Latency},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {101--109},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.101},
doi = {10.2197/IPSJTSLDM.7.101},
timestamp = {Tue, 26 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/JiangZW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/JoMF14,
author = {Satoshi Jo and
Takeshi Matsumoto and
Masahiro Fujita},
title = {SAT-based Automatic Rectification and Debugging of Combinational Circuits
with {LUT} Insertions},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {46--55},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.46},
doi = {10.2197/IPSJTSLDM.7.46},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/JoMF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KusakabeS14,
author = {Shingo Kusakabe and
Kenshu Seto},
title = {Forwarding Unit Generation for Loop Pipelining in High-level Synthesis},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {119--124},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.119},
doi = {10.2197/IPSJTSLDM.7.119},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KusakabeS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NagaiHI14,
author = {Eriko Nagai and
Atsushi Hashimoto and
Nagisa Ishiura},
title = {Reinforcing Random Testing of Arithmetic Optimization of {C} Compilers
by Scaling up Size and Number of Expressions},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {91--100},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.91},
doi = {10.2197/IPSJTSLDM.7.91},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NagaiHI14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Tomiyama14,
author = {Hiroyuki Tomiyama},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {1},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.1},
doi = {10.2197/IPSJTSLDM.7.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Tomiyama14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/WakabaWNI14,
author = {Yoichi Wakaba and
Shin'ichi Wakabayashi and
Shinobu Nagayama and
Masato Inagi},
title = {An Area Efficient Regular Expression Matching Engine Using Partial
Reconfiguration for Quick Pattern Updating},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {110--118},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.110},
doi = {10.2197/IPSJTSLDM.7.110},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/WakabaWNI14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhangMKA14,
author = {Hao Zhang and
Hiroki Matsutani and
Michihiro Koibuchi and
Hideharu Amano},
title = {Dynamic Power Consumption Optimization for Inductive-Coupling based
Wireless 3D NoCs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {27--36},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.27},
doi = {10.2197/IPSJTSLDM.7.27},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhangMKA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhuangS14,
author = {Jingcheng Zhuang and
Robert Bogdan Staszewski},
title = {All-Digital {RF} Phase-Locked Loops Exploiting Phase Prediction},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {7},
pages = {2--15},
year = {2014},
url = {https://doi.org/10.2197/ipsjtsldm.7.2},
doi = {10.2197/IPSJTSLDM.7.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhuangS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AkagicA13,
author = {Amila Akagic and
Hideharu Amano},
title = {Design and Implementation of IP-based iSCSI Offload Engine on an {FPGA}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {112--121},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.112},
doi = {10.2197/IPSJTSLDM.6.112},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AkagicA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AkasakaAYT13,
author = {Hiroyuki Akasaka and
Shin{-}ya Abe and
Masao Yanagisawa and
Nozomu Togawa},
title = {Energy-efficient High-level Synthesis for {HDR} Architectures with
Clock Gating Based on Concurrency-oriented Scheduling},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {101--111},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.101},
doi = {10.2197/IPSJTSLDM.6.101},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AkasakaAYT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/FujiwaraFT13,
author = {Katsuya Fujiwara and
Hideo Fujiwara and
Hideo Tamamoto},
title = {Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {27--33},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.27},
doi = {10.2197/IPSJTSLDM.6.27},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/FujiwaraFT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Hara-AzumiMTHT13,
author = {Yuko Hara{-}Azumi and
Toshinobu Matsuba and
Hiroyuki Tomiyama and
Shinya Honda and
Hiroaki Takada},
title = {Quantitative Evaluation of Resource Sharing in High-level Synthesis
Using Realistic Benchmarks},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {122--126},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.122},
doi = {10.2197/IPSJTSLDM.6.122},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Hara-AzumiMTHT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ItoK13,
author = {Kazuhito Ito and
Kazuhiko Kameda},
title = {A Method to Reduce Energy Consumption of Conditional Operations with
Execution Probabilities},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {60--70},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.60},
doi = {10.2197/IPSJTSLDM.6.60},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ItoK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/JiangZW13,
author = {Xin Jiang and
Ran Zhang and
Takahiro Watanabe},
title = {An Efficient Algorithm for 3D NoC Architecture Optimization},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {34--41},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.34},
doi = {10.2197/IPSJTSLDM.6.34},
timestamp = {Tue, 26 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/JiangZW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KatoS13,
author = {Yuta Kato and
Kenshu Seto},
title = {Loop Fusion with Outer Loop Shifting for High-level Synthesis},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {71--75},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.71},
doi = {10.2197/IPSJTSLDM.6.71},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KatoS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KuoL13,
author = {Huang{-}Chih Kuo and
Youn{-}Long Lin},
title = {{VLSI} Architecture Design for {H.264/AVC} Intra-frame Video Encoding},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {76--93},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.76},
doi = {10.2197/IPSJTSLDM.6.76},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KuoL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/LeeYKBS13,
author = {Yoonmyung Lee and
Dongmin Yoon and
Yejoong Kim and
David T. Blaauw and
Dennis Sylvester},
title = {Circuit and System Design Guidelines for Ultra-low Power Sensor Nodes},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {17--26},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.17},
doi = {10.2197/IPSJTSLDM.6.17},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/LeeYKBS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MizunoTTIKY13,
author = {Kosuke Mizuno and
Yosuke Terachi and
Kenta Takagi and
Shintaro Izumi and
Hiroshi Kawaguchi and
Masahiko Yoshimoto},
title = {An {FPGA} Implementation of a HOG-based Object Detection Processor},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {42--51},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.42},
doi = {10.2197/IPSJTSLDM.6.42},
timestamp = {Mon, 11 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/MizunoTTIKY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NakayaMSNS13,
author = {Shogo Nakaya and
Makoto Miyamura and
Noboru Sakimura and
Yuichi Nakamura and
Tadahiko Sugibayashi},
title = {A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {52--59},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.52},
doi = {10.2197/IPSJTSLDM.6.52},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/NakayaMSNS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ParkKPC13,
author = {Sangyoung Park and
Younghyun Kim and
Jaehyun Park and
Naehyuck Chang},
title = {Power Converter-aware Design of Electronics Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {2--16},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.2},
doi = {10.2197/IPSJTSLDM.6.2},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ParkKPC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SchmidtVFBWNSK13,
author = {Bernard Schmidt and
Carlos Villarraga and
Thomas Fehmel and
J{\"{o}}rg Bormann and
Markus Wedler and
Minh D. Nguyen and
Dominik Stoffel and
Wolfgang Kunz},
title = {A New Formal Verification Approach for Hardware-dependent Embedded
System Software},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {135--145},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.135},
doi = {10.2197/IPSJTSLDM.6.135},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SchmidtVFBWNSK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShengT13,
author = {Yiqiang Sheng and
Atsushi Takahashi},
title = {A New Variation of Adaptive Simulated Annealing for 2D/3D Packing
Optimization},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {94--100},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.94},
doi = {10.2197/IPSJTSLDM.6.94},
timestamp = {Mon, 01 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShengT13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TakataYM13,
author = {Taiga Takata and
Masayoshi Yoshimura and
Yusuke Matsunaga},
title = {Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation
in Sequential Circuits},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {127--134},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.127},
doi = {10.2197/IPSJTSLDM.6.127},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TakataYM13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Tomiyama13,
author = {Hiroyuki Tomiyama},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {6},
pages = {1},
year = {2013},
url = {https://doi.org/10.2197/ipsjtsldm.6.1},
doi = {10.2197/IPSJTSLDM.6.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Tomiyama13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AbeYT12,
author = {Shin{-}ya Abe and
Masao Yanagisawa and
Nozomu Togawa},
title = {Energy-efficient High-level Synthesis for {HDR} Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {106--117},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.106},
doi = {10.2197/IPSJTSLDM.5.106},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/AbeYT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KawashimaZTET12,
author = {Hirotaka Kawashima and
Gang Zeng and
Hideki Takase and
Masato Edahiro and
Hiroaki Takada},
title = {Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations
in {DEPS} Framework},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {133--142},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.133},
doi = {10.2197/IPSJTSLDM.5.133},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KawashimaZTET12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/LafiLJ12,
author = {Walid Lafi and
Didier Lattard and
Ahmed Amine Jerraya},
title = {A Stackable {LTE} Chip for Cost-effective 3D Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {2--13},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.2},
doi = {10.2197/IPSJTSLDM.5.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/LafiLJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NakataOKY12,
author = {Yohei Nakata and
Shunsuke Okumura and
Hiroshi Kawaguchi and
Masahiko Yoshimoto},
title = {0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T {SRAM}
and Its Testing Scheme},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {32--43},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.32},
doi = {10.2197/IPSJTSLDM.5.32},
timestamp = {Mon, 11 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/NakataOKY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ParkAICCCDN12,
author = {Sungho Park and
Ahmed Al{-}Maashri and
Kevin M. Irick and
Aarti Chandrashekhar and
Matthew Cotter and
Nandhini Chandramoorthy and
Michael DeBole and
Vijaykrishnan Narayanan},
title = {System-On-Chip for Biologically Inspired Vision Applications},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {71--95},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.71},
doi = {10.2197/IPSJTSLDM.5.71},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ParkAICCCDN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShibataAHTT12,
author = {Seiya Shibata and
Yuki Ando and
Shinya Honda and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {A Fast Performance Estimation Framework for System-Level Design Space
Exploration},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {44--54},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.44},
doi = {10.2197/IPSJTSLDM.5.44},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShibataAHTT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TakataM12,
author = {Taiga Takata and
Yusuke Matsunaga},
title = {A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects
in Combinational Circuits},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {55--62},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.55},
doi = {10.2197/IPSJTSLDM.5.55},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TakataM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Tomiyama12,
author = {Hiroyuki Tomiyama},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {1},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.1},
doi = {10.2197/IPSJTSLDM.5.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Tomiyama12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/XiaoILKNK12,
author = {Hao Xiao and
Tsuyoshi Isshiki and
Dongju Li and
Hiroaki Kunieda and
Yuko Nakase and
Sadahiro Kimura},
title = {Optimized Communication and Synchronization for Embedded Multiprocessors
Using {ASIP} Methodology},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {118--132},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.118},
doi = {10.2197/IPSJTSLDM.5.118},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/XiaoILKNK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YabuuchiK12,
author = {Michitarou Yabuuchi and
Kazutoshi Kobayashi},
title = {NBTI-Induced Delay Degradation Analysis of {FPGA} Routing Structures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {143--149},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.143},
doi = {10.2197/IPSJTSLDM.5.143},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YabuuchiK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Yan0W12,
author = {Tan Yan and
Qiang Ma and
Martin D. F. Wong},
title = {Advances in {PCB} Routing},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {14--22},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.14},
doi = {10.2197/IPSJTSLDM.5.14},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Yan0W12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YoshiharaYT12,
author = {Hiromine Yoshihara and
Masao Yanagisawa and
Nozomu Togawa},
title = {A Fast Weighted Adder by Reducing Partial Product for Reconstruction
in Super-Resolution},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {96--105},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.96},
doi = {10.2197/IPSJTSLDM.5.96},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/YoshiharaYT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YoshimuraAM12,
author = {Masayoshi Yoshimura and
Yusuke Akamine and
Yusuke Matsunaga},
title = {An Exact Estimation Algorithm of Error Propagation Probability for
Sequential Circuits},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {63--70},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.63},
doi = {10.2197/IPSJTSLDM.5.63},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YoshimuraAM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhaoCPZG12,
author = {Xiongxin Zhao and
Zhixiang Chen and
Xiao Peng and
Dajiang Zhou and
Satoshi Goto},
title = {{DVB-T2} {LDPC} Decoder with Perfect Conflict Resolution},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {5},
pages = {23--31},
year = {2012},
url = {https://doi.org/10.2197/ipsjtsldm.5.23},
doi = {10.2197/IPSJTSLDM.5.23},
timestamp = {Wed, 04 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhaoCPZG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AxerDNSSE11,
author = {Philip Axer and
Jonas Diemer and
Mircea Negrean and
Maurice Sebastian and
Simon Schliecker and
Rolf Ernst},
title = {Mastering MPSoCs for Mixed-critical Applications},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {91--116},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.91},
doi = {10.2197/IPSJTSLDM.4.91},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AxerDNSSE11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Choi11,
author = {Kiyoung Choi},
title = {Coarse-Grained Reconfigurable Array: Architecture and Application
Mapping},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {31--46},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.31},
doi = {10.2197/IPSJTSLDM.4.31},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Choi11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/InoueK11,
author = {Keisuke Inoue and
Mineo Kaneko},
title = {Framework for Latch-based High-level Synthesis Using Minimum-delay
Compensation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {232--244},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.232},
doi = {10.2197/IPSJTSLDM.4.232},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/InoueK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KajiharaOY11,
author = {Seiji Kajihara and
Satoshi Ohtake and
Tomokazu Yoneda},
title = {Delay Testing: Improving Test Quality and Avoiding Over-testing},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {117--130},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.117},
doi = {10.2197/IPSJTSLDM.4.117},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KajiharaOY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KakiuchiNHTN11,
author = {Yosuke Kakiuchi and
Tomofumi Nakagawa and
Kiyoharu Hamaguchi and
Tadaaki Tanimoto and
Masaki Nakanishi},
title = {Symbolic Discord Computation for Efficient Analysis of Message Sequence
Charts},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {210--221},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.210},
doi = {10.2197/IPSJTSLDM.4.210},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KakiuchiNHTN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KaradumanSA11,
author = {Arda Karaduman and
Iver Stubdal and
Hideharu Amano},
title = {Design and Implementation of Echo Instructions for an Embedded Processor},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {222--231},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.222},
doi = {10.2197/IPSJTSLDM.4.222},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KaradumanSA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KawashimaT11,
author = {Hirotaka Kawashima and
Naofumi Takagi},
title = {Partial Product Generation Utilizing the Sum of Operands for Reduced
Area Parallel Multipliers},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {131--139},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.131},
doi = {10.2197/IPSJTSLDM.4.131},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/KawashimaT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KrishnamoorthyDVAFNN11,
author = {Ratna Krishnamoorthy and
Saptarsi Das and
Keshavan Varadarajan and
Mythri Alle and
Masahiro Fujita and
Soumitra Kumar Nandy and
Ranjani Narayan},
title = {Data Flow Graph Partitioning Algorithms and Their Evaluations for
Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable
Architecture},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {193--209},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.193},
doi = {10.2197/IPSJTSLDM.4.193},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KrishnamoorthyDVAFNN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/LeiIUNKNA11,
author = {Zhao Lei and
Daisuke Ikebuchi and
Kimiyoshi Usami and
Mitaro Namiki and
Masaaki Kondo and
Hiroshi Nakamura and
Hideharu Amano},
title = {Design and Implementation Fine-grained Power Gating on Microprocessor
Functional Units},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {182--192},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.182},
doi = {10.2197/IPSJTSLDM.4.182},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/LeiIUNKNA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MatsumotoNI11,
author = {Kiyonori Matsumoto and
Kazuteru Namba and
Hideo Ito},
title = {Scan {FF} Reordering for Test Volume Reduction in Chiba-scan Architecture},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {140--149},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.140},
doi = {10.2197/IPSJTSLDM.4.140},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MatsumotoNI11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MitraCHKLLLLMMPPW011,
author = {Subhasish Mitra and
Hyungmin Cho and
Ted Hong and
Young Moon Kim and
Hsiao{-}Heng Lee and
Larkhoon Leem and
Yanjing Li and
David Lin and
Evelyn Mintarno and
Diana Mui and
Sung{-}Boem Park and
Nishant Patil and
Hai Wei and
Jie Zhang},
title = {Robust System Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {2--30},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.2},
doi = {10.2197/IPSJTSLDM.4.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MitraCHKLLLLMMPPW011.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NaraTYO11,
author = {Ryuta Nara and
Nozomu Togawa and
Masao Yanagisawa and
Tatsuo Ohtsuki},
title = {Scan Vulnerability in Elliptic Curve Cryptosystems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {47--59},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.47},
doi = {10.2197/IPSJTSLDM.4.47},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/NaraTYO11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NoguchiIFONKY11,
author = {Hiroki Noguchi and
Yusuke Iguchi and
Hidehiro Fujiwara and
Shunsuke Okumura and
Koji Nii and
Hiroshi Kawaguchi and
Masahiko Yoshimoto},
title = {Design Choice in 45-nm Dual-Port {SRAM} - 8T, 10T Single End, and
10T Differential},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {80--90},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.80},
doi = {10.2197/IPSJTSLDM.4.80},
timestamp = {Mon, 11 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/NoguchiIFONKY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera11,
author = {Hidetoshi Onodera},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {1},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.1},
doi = {10.2197/IPSJTSLDM.4.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TanakaYOT11,
author = {Sho Tanaka and
Masao Yanagisawa and
Tatsuo Ohtsuki and
Nozomu Togawa},
title = {A Fault-Secure High-Level Synthesis Algorithm for {RDR} Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {150--165},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.150},
doi = {10.2197/IPSJTSLDM.4.150},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/TanakaYOT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TawadaYOT11,
author = {Masashi Tawada and
Masao Yanagisawa and
Tatsuo Ohtsuki and
Nozomu Togawa},
title = {Exact, Fast and Flexible {L1} Cache Configuration Simulation for Embedded
Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {166--181},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.166},
doi = {10.2197/IPSJTSLDM.4.166},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/TawadaYOT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TsukamotoYOT11,
author = {Youhei Tsukamoto and
Masao Yanagisawa and
Tatsuo Ohtsuki and
Nozomu Togawa},
title = {A Fast Selector-Based Subtract-Multiplication Unit and Its Application
to Butterfly Unit},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {60--69},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.60},
doi = {10.2197/IPSJTSLDM.4.60},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/TsukamotoYOT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YoshidaF11,
author = {Hiroaki Yoshida and
Masahiro Fujita},
title = {Exact Minimum Factoring of Incompletely Specified Logic Functions
via Quantified Boolean Satisfiability},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {70--79},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.70},
doi = {10.2197/IPSJTSLDM.4.70},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YoshidaF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ChenZPZG10,
author = {Zhixiang Chen and
Xiongxin Zhao and
Xiao Peng and
Dajiang Zhou and
Satoshi Goto},
title = {A High Parallelism {LDPC} Decoder with an Early Stopping Criterion
for WiMax and WiFi Application},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {292--302},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.292},
doi = {10.2197/IPSJTSLDM.3.292},
timestamp = {Wed, 04 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ChenZPZG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ChengC10,
author = {Kwang{-}Ting (Tim) Cheng and
Hsiu{-}Ming (Sherman) Chang},
title = {Recent Advances in Analog, Mixed-Signal, and {RF} Testing},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {19--46},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.19},
doi = {10.2197/IPSJTSLDM.3.19},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/ChengC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/CongL10,
author = {Jason Cong and
Guojie Luo},
title = {Advances and Challenges in 3D Physical Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {2--18},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.2},
doi = {10.2197/IPSJTSLDM.3.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/CongL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HamaguchiMK10,
author = {Kiyoharu Hamaguchi and
Kazuya Masuda and
Toshinobu Kashiwabara},
title = {Approximate Model Checking Using a Subset of First-order Logic},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {268--282},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.268},
doi = {10.2197/IPSJTSLDM.3.268},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HamaguchiMK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HeZZG10,
author = {Xun He and
Dajiang Zhou and
Jinjia Zhou and
Satoshi Goto},
title = {High Profile Intra Prediction Architecture for {UHD} {H.264} Decoder},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {303--313},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.303},
doi = {10.2197/IPSJTSLDM.3.303},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HeZZG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ImaiTSI10,
author = {Masaharu Imai and
Yoshinori Takeuchi and
Keishi Sakanushi and
Nagisa Ishiura},
title = {Advantage and Possibility of Application-domain Specific Instruction-set
Processor {(ASIP)}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {161--178},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.161},
doi = {10.2197/IPSJTSLDM.3.161},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ImaiTSI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/InagiTN10,
author = {Masato Inagi and
Yasuhiro Takashima and
Yuichi Nakamura},
title = {Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA
Prototyping Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {81--90},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.81},
doi = {10.2197/IPSJTSLDM.3.81},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/InagiTN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/IwatoSTI10,
author = {Hirofumi Iwato and
Keishi Sakanushi and
Yoshinori Takeuchi and
Masaharu Imai},
title = {A Low-power {ASIP} Generation Method by Extracting Minimum Execution
Conditions},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {222--233},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.222},
doi = {10.2197/IPSJTSLDM.3.222},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/IwatoSTI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KhanILK10,
author = {Arif Ullah Khan and
Tsuyoshi Isshiki and
Dongju Li and
Hiroaki Kunieda},
title = {A Unified Performance Estimation Method for Hardware and Software
Components in Multiprocessor System-On-Chips},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {194--206},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.194},
doi = {10.2197/IPSJTSLDM.3.194},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KhanILK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KumuraTITI10,
author = {Takahiro Kumura and
Soichiro Taga and
Nagisa Ishiura and
Yoshinori Takeuchi and
Masaharu Imai},
title = {Software Development Tool Generation Method Suitable for Instruction
Set Extension of Embedded Processors},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {207--221},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.207},
doi = {10.2197/IPSJTSLDM.3.207},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KumuraTITI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MatsumotoNF10,
author = {Takeshi Matsumoto and
Tasuku Nishihara and
Masahiro Fujita},
title = {Performance Estimation with Automatic False-Path Detection for System-Level
Designs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {69--80},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.69},
doi = {10.2197/IPSJTSLDM.3.69},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MatsumotoNF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NagayamaSB10,
author = {Shinobu Nagayama and
Tsutomu Sasao and
Jon T. Butler},
title = {Programmable Architectures and Design Methods for Two-Variable Numeric
Function Generators},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {118--129},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.118},
doi = {10.2197/IPSJTSLDM.3.118},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NagayamaSB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NomotoKO10,
author = {Shouhei Nomoto and
Shorin Kyo and
Shin'ichiro Okazaki},
title = {Performance Evaluation of a Dynamically Switchable {SIMD/MIMD} Processor
by Using an Image Recognition Application},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {47--56},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.47},
doi = {10.2197/IPSJTSLDM.3.47},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NomotoKO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/OkuKSMW10,
author = {Shinji Oku and
Seiji Kajihara and
Yasuo Sato and
Kohei Miyase and
Xiaoqing Wen},
title = {On Delay Test Quality for Test Cubes},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {283--291},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.283},
doi = {10.2197/IPSJTSLDM.3.283},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/OkuKSMW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera10,
author = {Hidetoshi Onodera},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {1},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.1},
doi = {10.2197/IPSJTSLDM.3.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SanderBR10,
author = {Bj{\"{o}}rn Sander and
Andreas Bernauer and
Wolfgang Rosenstiel},
title = {Design and Run-time Reliability at the Electronic System Level},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {140--160},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.140},
doi = {10.2197/IPSJTSLDM.3.140},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SanderBR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SchaferS10,
author = {Benjamin Carri{\'{o}}n Sch{\"{a}}fer and
Majid Sarrafzadeh},
title = {Semi-Automatic Control Unit Generation for Complex {VLSI} Designs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {234--243},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.234},
doi = {10.2197/IPSJTSLDM.3.234},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SchaferS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SetoF10,
author = {Kenshu Seto and
Masahiro Fujita},
title = {Custom Instruction Generation for Configurable Processors with Limited
Numbers of Operands},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {57--68},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.57},
doi = {10.2197/IPSJTSLDM.3.57},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SetoF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SetoI10,
author = {Hidekazu Seto and
Kazuhito Ito},
title = {A Resource Binding Method to Reduce Data Communication Power Dissipation
on {LSI}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {257--267},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.257},
doi = {10.2197/IPSJTSLDM.3.257},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SetoI10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShibataAHTT10,
author = {Seiya Shibata and
Yuki Ando and
Shinya Honda and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {Efficient Design Space Exploration at System Level with Automatic
Profiler Instrumentation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {179--193},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.179},
doi = {10.2197/IPSJTSLDM.3.179},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShibataAHTT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShimizuHK10,
author = {Hiroaki Shimizu and
Kiyoharu Hamaguchi and
Toshinobu Kashiwabara},
title = {Approximate Invariant Property Checking Using Term-Height Reduction
for a Subset of First-Order Logic},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {105--117},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.105},
doi = {10.2197/IPSJTSLDM.3.105},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShimizuHK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/SunagawaTTKO10,
author = {Hiroki Sunagawa and
Haruhiko Terada and
Akira Tsuchiya and
Kazutoshi Kobayashi and
Hidetoshi Onodera},
title = {Effect of Regularity-Enhanced Layout on Variability and Circuit Performance
of Standard Cells},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {130--139},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.130},
doi = {10.2197/IPSJTSLDM.3.130},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/SunagawaTTKO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ToiNKAW10,
author = {Takao Toi and
Noritsugu Nakamura and
Yoshinosuke Kato and
Toru Awashima and
Kazutoshi Wakabayashi},
title = {High-level Synthesis Challenges for Mapping a Complete Program on
a Dynamically Reconfigurable Processor},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {91--104},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.91},
doi = {10.2197/IPSJTSLDM.3.91},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ToiNKAW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YamadaOOIOYNFHASO10,
author = {Hideki Yamada and
Yui Ogawa and
Tomonori Ooya and
Tomoya Ishimori and
Yasunori Osana and
Masato Yoshimi and
Yuri Nishikawa and
Akira Funahashi and
Noriko Hiroi and
Hideharu Amano and
Yuichiro Shibata and
Kiyoshi Oguri},
title = {Automatic Pipeline Construction Focused on Similarity of Rate Law
Functions for an FPGA-based Biochemical Simulator},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {3},
pages = {244--256},
year = {2010},
url = {https://doi.org/10.2197/ipsjtsldm.3.244},
doi = {10.2197/IPSJTSLDM.3.244},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/YamadaOOIOYNFHASO10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ChangJC09,
author = {Yao{-}Wen Chang and
Zhe{-}Wei Jiang and
Tung{-}Chieh Chen},
title = {Essential Issues in Analytical Placement Algorithms},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {145--166},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.145},
doi = {10.2197/IPSJTSLDM.2.145},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ChangJC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/DongN09,
author = {Qing Dong and
Shigetoshi Nakatake},
title = {Structured Placement with Topological Regularity Evaluation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {222--238},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.222},
doi = {10.2197/IPSJTSLDM.2.222},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/DongN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Fujita09,
author = {Masahiro Fujita},
title = {Trends in Formal Verification Techniques for C-based Hardware Designs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {2--17},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.2},
doi = {10.2197/IPSJTSLDM.2.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Fujita09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/GeCY09,
author = {Liangwei Ge and
Song Chen and
Takeshi Yoshimura},
title = {Exploration of Schedule Space by Random Walk},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {30--42},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.30},
doi = {10.2197/IPSJTSLDM.2.30},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/GeCY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HamadaSKSYMN09,
author = {Naohiro Hamada and
Yuki Shiga and
Takao Konishi and
Hiroshi Saito and
Tomohiro Yoneda and
Chris J. Myers and
Takashi Nanya},
title = {A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data
Implementation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {64--79},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.64},
doi = {10.2197/IPSJTSLDM.2.64},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HamadaSKSYMN09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HigamiSTKT09,
author = {Yoshinobu Higami and
Kewal K. Saluja and
Hiroshi Takahashi and
Shin{-}ya Kobayashi and
Yuzo Takamatsu},
title = {An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {250--262},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.250},
doi = {10.2197/IPSJTSLDM.2.250},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HigamiSTKT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HiromotoON09,
author = {Masayuki Hiromoto and
Hiroyuki Ochi and
Yukihiro Nakamura},
title = {An Asynchronous IEEE-754-standard Single-precision Floating-point
Divider for {FPGA}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {103--113},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.103},
doi = {10.2197/IPSJTSLDM.2.103},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/HiromotoON09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/HuangLI09,
author = {Yiqing Huang and
Qin Liu and
Takeshi Ikenaga},
title = {Macroblock Feature Based Adaptive Propagate Partial {SAD} Architecture
for {HDTV} Application},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {263--273},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.263},
doi = {10.2197/IPSJTSLDM.2.263},
timestamp = {Mon, 23 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/HuangLI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/InagakiSNMI09,
author = {Ryosuke Inagaki and
Norio Sadachika and
Dondee Navarro and
Mitiko Miura{-}Mattausch and
Yasuaki Inoue},
title = {A GIDL-Current Model for Advanced {MOSFET} Technologies without Binning},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {93--102},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.93},
doi = {10.2197/IPSJTSLDM.2.93},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/InagakiSNMI09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ItoS09,
author = {Kazuhito Ito and
Hidekazu Seto},
title = {Reducing Power Dissipation of Data Communications on {LSI} with Scheduling
Exploration},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {53--63},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.53},
doi = {10.2197/IPSJTSLDM.2.53},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ItoS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/JiLIG09,
author = {Wen Ji and
Xing Li and
Takeshi Ikenaga and
Satoshi Goto},
title = {A High Throughput {LDPC} Decoder Design Based on Novel Delta-value
Message-passing Schedule},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {122--130},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.122},
doi = {10.2197/IPSJTSLDM.2.122},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/JiLIG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KodamaM09,
author = {Sho Kodama and
Yusuke Matsunaga},
title = {Binding Refinement for Multiplexer Reduction},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {43--52},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.43},
doi = {10.2197/IPSJTSLDM.2.43},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KodamaM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KunduLG09,
author = {Sudipta Kundu and
Sorin Lerner and
Rajesh Gupta},
title = {High-Level Verification},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {131--144},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.131},
doi = {10.2197/IPSJTSLDM.2.131},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KunduLG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MatsumuraIY09,
author = {Tadayuki Matsumura and
Tohru Ishihara and
Hiroto Yasuura},
title = {An Optimization Technique for Low-Energy Embedded Memory Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {239--249},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.239},
doi = {10.2197/IPSJTSLDM.2.239},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/MatsumuraIY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/MatsunagaKM09,
author = {Taeko Matsunaga and
Shinji Kimura and
Yusuke Matsunaga},
title = {Framework for Parallel Prefix Adder Synthesis Considering Switching
Activities},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {212--221},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.212},
doi = {10.2197/IPSJTSLDM.2.212},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/MatsunagaKM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera09,
author = {Hidetoshi Onodera},
title = {Message from the Editor-in-Chief},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {1},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.1},
doi = {10.2197/IPSJTSLDM.2.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TakamiyaS09,
author = {Makoto Takamiya and
Takayasu Sakurai},
title = {Low Power {VLSI} Circuit Design with Fine-Grain Voltage Engineering},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {18--29},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.18},
doi = {10.2197/IPSJTSLDM.2.18},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TakamiyaS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TakaseTT09,
author = {Hideki Takase and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {Partitioning and Allocation of Scratch-Pad Memory in Priority-Based
Multi-Task Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {180--188},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.180},
doi = {10.2197/IPSJTSLDM.2.180},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TakaseTT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TakataM09,
author = {Taiga Takata and
Yusuke Matsunaga},
title = {Area Recovery under Depth Constraint for Technology Mapping for LUT-based
FPGAs},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {200--211},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.200},
doi = {10.2197/IPSJTSLDM.2.200},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TakataM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TakeuchiHK09,
author = {Sho Takeuchi and
Kiyoharu Hamaguchi and
Toshinobu Kashiwabara},
title = {Checker Generation of Assertions with Local Variables for Model Checking},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {80--92},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.80},
doi = {10.2197/IPSJTSLDM.2.80},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TakeuchiHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/WeiIG09,
author = {Xianghui Wei and
Takeshi Ikenaga and
Satoshi Goto},
title = {A Low Bandwidth Integer Motion Estimation Module for {MPEG-2} to {H.264}
Transcoding},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {114--121},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.114},
doi = {10.2197/IPSJTSLDM.2.114},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/WeiIG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/YamaguchiIIY09,
author = {Seiichiro Yamaguchi and
Yuriko Ishitobi and
Tohru Ishihara and
Hiroto Yasuura},
title = {Single-Cycle-Accessible Two-Level Caches and Compilation Technique
for Energy Reducion},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {189--199},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.189},
doi = {10.2197/IPSJTSLDM.2.189},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/YamaguchiIIY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZengTT09,
author = {Gang Zeng and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {A Generalized Framework for Energy Savings in Hard Real-Time Embedded
Systems},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {2},
pages = {167--179},
year = {2009},
url = {https://doi.org/10.2197/ipsjtsldm.2.167},
doi = {10.2197/IPSJTSLDM.2.167},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZengTT09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/GeCNY08,
author = {Liangwei Ge and
Song Chen and
Yuichi Nakamura and
Takeshi Yoshimura},
title = {A Synthesis Method of General Floating-Point Arithmetic Units by Aligned
Partition},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {67--77},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.67},
doi = {10.2197/IPSJTSLDM.1.67},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/GeCNY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KajiharaMYWFHA08,
author = {Seiji Kajihara and
Shohei Morishima and
Masahiro Yamamoto and
Xiaoqing Wen and
Masayasu Fukunaga and
Kazumi Hatayama and
Takashi Aikyo},
title = {Estimation of Delay Test Quality and Its Application to Test Generation},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {104--115},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.104},
doi = {10.2197/IPSJTSLDM.1.104},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KajiharaMYWFHA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/KatohNI08,
author = {Kentaroh Katoh and
Kazuteru Namba and
Hideo Ito},
title = {Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops
with Delay Fault Testability},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {91--103},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.91},
doi = {10.2197/IPSJTSLDM.1.91},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/KatohNI08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NakashimaKN08,
author = {Hiroshi Nakashima and
Masahiro Konishi and
Takashi Nakada},
title = {A Simulation-Based Analysis for Worst Case Delay of Single and Multiple
Interruptions},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {33--47},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.33},
doi = {10.2197/IPSJTSLDM.1.33},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NakashimaKN08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/OhchiKTYO08,
author = {Akira Ohchi and
Shunitsu Kohara and
Nozomu Togawa and
Masao Yanagisawa and
Tatsuo Ohtsuki},
title = {Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register
Architectures},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {78--90},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.78},
doi = {10.2197/IPSJTSLDM.1.78},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/OhchiKTYO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Onodera08,
author = {Hidetoshi Onodera},
title = {Welcome to {TSLDM} - {A} New Open-Access Online Journal from {IPSJ}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {1},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.1},
doi = {10.2197/IPSJTSLDM.1.1},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Onodera08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/PasrichaD08,
author = {Sudeep Pasricha and
Nikil D. Dutt},
title = {Trends in Emerging On-Chip Interconnect Technologies},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {2--17},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.2},
doi = {10.2197/IPSJTSLDM.1.2},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/PasrichaD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Sapatnekar08,
author = {Sachin S. Sapatnekar},
title = {Variability and Statistical Design},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {18--32},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.18},
doi = {10.2197/IPSJTSLDM.1.18},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Sapatnekar08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ShibataHHTT08,
author = {Seiya Shibata and
Shinya Honda and
Yuko Hara and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {Embedded System Covalidation with {RTOS} Model and {FPGA}},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {126--130},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.126},
doi = {10.2197/IPSJTSLDM.1.126},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ShibataHHTT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TanakaNA08,
author = {Katsunori Tanaka and
Yuichi Nakamura and
Atsushi Atarashi},
title = {A Study of Multi-core Processor Design with Asynchronous Interconnect
Using Synchronous Design Tools},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {58--66},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.58},
doi = {10.2197/IPSJTSLDM.1.58},
timestamp = {Fri, 10 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ipsj/TanakaNA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/TeradaFTO08,
author = {Haruhiko Terada and
Takayuki Fukuoka and
Akira Tsuchiya and
Hidetoshi Onodera},
title = {Accurate Estimation of the Worst-case Delay in Statistical Static
Timing Analysis},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {116--125},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.116},
doi = {10.2197/IPSJTSLDM.1.116},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/TeradaFTO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZengTT08,
author = {Gang Zeng and
Hiroyuki Tomiyama and
Hiroaki Takada},
title = {Dynamic Power Management for Embedded System Idle State in the Presence
of Periodic Interrupt Services},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {1},
pages = {48--57},
year = {2008},
url = {https://doi.org/10.2197/ipsjtsldm.1.48},
doi = {10.2197/IPSJTSLDM.1.48},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZengTT08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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