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@article{DBLP:journals/integration/AkinBSL14,
author = {Abdulkadir Akin and
Ipek Baz and
Alexandre Schmid and
Yusuf Leblebici},
title = {Dynamically adaptive real-time disparity estimation hardware using
iterative refinement},
journal = {Integr.},
volume = {47},
number = {3},
pages = {365--376},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.002},
doi = {10.1016/J.VLSI.2013.11.002},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AkinBSL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AsyaeiP14,
author = {Mohammad Asyaei and
Ali Peiravi},
title = {Low power wide gates for modern power efficient processors},
journal = {Integr.},
volume = {47},
number = {2},
pages = {272--283},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.08.005},
doi = {10.1016/J.VLSI.2013.08.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AsyaeiP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AyalaO14,
author = {Jos{\'{e}} L. Ayala and
Katzalin Olcoz},
title = {{VLSI} for the new era},
journal = {Integr.},
volume = {47},
number = {3},
pages = {295},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.12.002},
doi = {10.1016/J.VLSI.2013.12.002},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/AyalaO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BasyurtA14,
author = {Pinar Basak Basyurt and
Devrim Yilmaz Aksin},
title = {Untrimmed 6.2 ppm/{\textdegree}C bulk-isolated curvature-corrected
bandgap voltage reference},
journal = {Integr.},
volume = {47},
number = {1},
pages = {30--37},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.03.005},
doi = {10.1016/J.VLSI.2013.03.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BasyurtA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BelghadrJ14,
author = {Armin Belghadr and
Ali Jahanian},
title = {Metro-on-FPGA: {A} feasible solution to improve the congestion and
routing resource management in future FPGAs},
journal = {Integr.},
volume = {47},
number = {1},
pages = {96--104},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.07.002},
doi = {10.1016/J.VLSI.2013.07.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BelghadrJ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BrelsfordLF14,
author = {Kevin Brelsford and
Seraf{\'{\i}}n A. P{\'{e}}rez L{\'{o}}pez and
Santiago Fern{\'{a}}ndez{-}Gomez},
title = {Energy efficient computation: {A} silicon perspective},
journal = {Integr.},
volume = {47},
number = {1},
pages = {1--11},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.07.001},
doi = {10.1016/J.VLSI.2013.07.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BrelsfordLF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChenHX14,
author = {Xi Chen and
Jiang Hu and
Ning Xu},
title = {Regularity-constrained floorplanning for multi-core processors},
journal = {Integr.},
volume = {47},
number = {1},
pages = {86--95},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.05.002},
doi = {10.1016/J.VLSI.2013.05.002},
timestamp = {Tue, 02 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChenHX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChengXRGGH14,
author = {Lerong Cheng and
Wenyao Xu and
Fengbo Ren and
Fang Gong and
Puneet Gupta and
Lei He},
title = {Statistical timing and power analysis of {VLSI} considering non-linear
dependence},
journal = {Integr.},
volume = {47},
number = {4},
pages = {487--498},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.12.004},
doi = {10.1016/J.VLSI.2013.12.004},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChengXRGGH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChowLYS14,
author = {Wing{-}Kai Chow and
Liang Li and
Evangeline F. Y. Young and
Chiu{-}Wing Sham},
title = {Obstacle-avoiding rectilinear Steiner tree construction in sequential
and parallel approach},
journal = {Integr.},
volume = {47},
number = {1},
pages = {105--114},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.08.001},
doi = {10.1016/J.VLSI.2013.08.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChowLYS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/CicekPD14,
author = {Ihsan {\c{C}}i{\c{c}}ek and
Ali Emre Pusane and
G{\"{u}}nhan D{\"{u}}ndar},
title = {A novel design method for discrete time chaos based true random number
generators},
journal = {Integr.},
volume = {47},
number = {1},
pages = {38--47},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.06.003},
doi = {10.1016/J.VLSI.2013.06.003},
timestamp = {Wed, 07 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/CicekPD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/DorrigivJ14,
author = {Morteza Dorrigiv and
Ghassem Jaberipur},
title = {Low area/power decimal addition with carry-select correction and carry-select
sum-digits},
journal = {Integr.},
volume = {47},
number = {4},
pages = {443--451},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2014.01.004},
doi = {10.1016/J.VLSI.2014.01.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/DorrigivJ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EerolaN14,
author = {Ville Eerola and
Jari Nurmi},
title = {High-level parameterizable area estimation modeling for {ASIC} designs},
journal = {Integr.},
volume = {47},
number = {4},
pages = {461--475},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2014.01.002},
doi = {10.1016/J.VLSI.2014.01.002},
timestamp = {Wed, 16 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/EerolaN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/EfstathiouMAP14,
author = {Constantinos Efstathiou and
Nikos K. Moshopoulos and
Nicholas Axelos and
Kiamal Z. Pekmestzi},
title = {Efficient modulo 2\({}^{\mbox{n}}\)+1 multiply and multiply-add units
based on modified Booth encoding},
journal = {Integr.},
volume = {47},
number = {1},
pages = {140--147},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.04.001},
doi = {10.1016/J.VLSI.2013.04.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/EfstathiouMAP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Elrabaa14,
author = {Muhammad E. S. Elrabaa},
title = {A portable high-frequency digitally controlled oscillator {(DCO)}},
journal = {Integr.},
volume = {47},
number = {3},
pages = {339--346},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.009},
doi = {10.1016/J.VLSI.2013.10.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Elrabaa14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FarshidiRBW14,
author = {Amin Farshidi and
Logan M. Rakai and
Laleh Behjat and
David T. Westwick},
title = {Optimal gate sizing using a self-tuning multi-objective framework},
journal = {Integr.},
volume = {47},
number = {3},
pages = {347--355},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.008},
doi = {10.1016/J.VLSI.2013.10.008},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/FarshidiRBW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FathipourSMA14,
author = {Rasoul Fathipour and
Alireza Saberkari and
Herminio Mart{\'{\i}}nez and
Eduard Alarc{\'{o}}n},
title = {High slew rate current mode transconductance error amplifier for low
quiescent current output-capacitorless {CMOS} {LDO} regulator},
journal = {Integr.},
volume = {47},
number = {2},
pages = {204--212},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.005},
doi = {10.1016/J.VLSI.2013.10.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FathipourSMA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/FerentD14,
author = {Cristian Ferent and
Alex Doboli},
title = {Analog circuit design space description based on ordered clustering
of feature uniqueness and similarity},
journal = {Integr.},
volume = {47},
number = {2},
pages = {213--231},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.08.004},
doi = {10.1016/J.VLSI.2013.08.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/FerentD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ForoutanTNM14,
author = {Vahid Foroutan and
MohammadReza Taheri and
Keivan Navi and
Arash Azizi Mazreah},
title = {Design of two Low-Power full adder cells using {GDI} structure and
hybrid {CMOS} logic style},
journal = {Integr.},
volume = {47},
number = {1},
pages = {48--61},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.05.001},
doi = {10.1016/J.VLSI.2013.05.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ForoutanTNM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GenoveseNCPS14,
author = {Mariangela Genovese and
Ettore Napoli and
Davide De Caro and
Nicola Petra and
Antonio G. M. Strollo},
title = {Analysis and comparison of Direct Digital Frequency Synthesizers implemented
on {FPGA}},
journal = {Integr.},
volume = {47},
number = {2},
pages = {261--271},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.09.001},
doi = {10.1016/J.VLSI.2013.09.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GenoveseNCPS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GuoCGZ14,
author = {Xiaolu Guo and
Mario R. Casu and
Mariagrazia Graziano and
Maurizio Zamboni},
title = {Simulation and design of an {UWB} imaging system for breast cancer
detection},
journal = {Integr.},
volume = {47},
number = {4},
pages = {548--559},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2014.02.001},
doi = {10.1016/J.VLSI.2014.02.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GuoCGZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/HabibiBM14,
author = {Mehdi Habibi and
Alireza Bafandeh and
Muhammad Ali Montazerolghaem},
title = {A digital array based bit serial processor for arbitrary window size
kernel convolution in vision sensors},
journal = {Integr.},
volume = {47},
number = {4},
pages = {417--430},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.007},
doi = {10.1016/J.VLSI.2013.11.007},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/HabibiBM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JoLHC14,
author = {Manhwee Jo and
Dongwook Lee and
Kyuseung Han and
Kiyoung Choi},
title = {Design of a coarse-grained reconfigurable architecture with floating-point
support and comparative study},
journal = {Integr.},
volume = {47},
number = {2},
pages = {232--241},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.08.003},
doi = {10.1016/J.VLSI.2013.08.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JoLHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KoukounisTPT14,
author = {Dimitris Koukounis and
Christos Ttofis and
Agathoklis Papadopoulos and
Theocharis Theocharides},
title = {A high performance hardware architecture for portable, low-power retinal
vessel segmentation},
journal = {Integr.},
volume = {47},
number = {3},
pages = {377--386},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.005},
doi = {10.1016/J.VLSI.2013.11.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KoukounisTPT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KuangWKYJ14,
author = {Shiann{-}Rong Kuang and
Kun{-}Yi Wu and
Bao{-}Chen Ke and
Jia{-}Huei Yeh and
Hao{-}Yi Jheng},
title = {Efficient architecture and hardware implementation of hybrid fuzzy-Kalman
filter for workload prediction},
journal = {Integr.},
volume = {47},
number = {4},
pages = {408--416},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.006},
doi = {10.1016/J.VLSI.2013.11.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KuangWKYJ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/KunduM14,
author = {Sudip Kundu and
Pradip Mandal},
title = {{ISGP:} Iterative sequential geometric programming for precise and
robust {CMOS} analog circuit sizing},
journal = {Integr.},
volume = {47},
number = {4},
pages = {510--531},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2014.01.001},
doi = {10.1016/J.VLSI.2014.01.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/KunduM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LeeK14,
author = {Byunghyun Lee and
Taewhan Kim},
title = {Algorithms for {TSV} resource sharing and optimization in designing
3D stacked ICs},
journal = {Integr.},
volume = {47},
number = {2},
pages = {184--194},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.001},
doi = {10.1016/J.VLSI.2013.11.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LeeK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LemberskiF14,
author = {Igor Lemberski and
Petr Fiser},
title = {Dual-rail asynchronous logic multi-level implementation},
journal = {Integr.},
volume = {47},
number = {1},
pages = {148--159},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.02.002},
doi = {10.1016/J.VLSI.2013.02.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LemberskiF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/LiuTWH014,
author = {Zao Liu and
Sheldon X.{-}D. Tan and
Hai Wang and
Yingbo Hua and
Ashish Gupta},
title = {Compact thermal modeling for packaged microprocessor design with practical
power maps},
journal = {Integr.},
volume = {47},
number = {1},
pages = {71--85},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.07.003},
doi = {10.1016/J.VLSI.2013.07.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/LiuTWH014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MarquezMCGLSG14,
author = {Fernando J. Marquez and
Fernando Mu{\~{n}}oz and
Ram{\'{o}}n Gonz{\'{a}}lez Carvajal and
Jos{\'{e}} Ram{\'{o}}n Garc{\'{\i}}a Oya and
Enrique L{\'{o}}pez{-}Morillo and
Antonio Jes{\'{u}}s Torralba Silgado and
Juan Antonio G{\'{o}}mez Gal{\'{a}}n},
title = {A novel autozeroing technique for flash Analog-to-Digital converters},
journal = {Integr.},
volume = {47},
number = {1},
pages = {23--29},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.06.002},
doi = {10.1016/J.VLSI.2013.06.002},
timestamp = {Tue, 08 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MarquezMCGLSG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MartinsLCH14,
author = {Ricardo Martins and
Nuno Louren{\c{c}}o and
Ant{\'{o}}nio Canelas and
Nuno Horta},
title = {Electromigration-aware analog Router with multilayer multiport terminal
structures},
journal = {Integr.},
volume = {47},
number = {4},
pages = {532--547},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2014.02.003},
doi = {10.1016/J.VLSI.2014.02.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MartinsLCH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Mesgarzadeh14,
author = {Behzad Mesgarzadeh},
title = {Simultaneous switching noise reduction by resonant clock distribution
networks},
journal = {Integr.},
volume = {47},
number = {2},
pages = {242--249},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.002},
doi = {10.1016/J.VLSI.2013.10.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Mesgarzadeh14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MichailATG14,
author = {Harris E. Michail and
Georgios Athanasiou and
George Theodoridis and
Costas E. Goutis},
title = {On the development of high-throughput and area-efficient multi-mode
cryptographic hash designs in FPGAs},
journal = {Integr.},
volume = {47},
number = {4},
pages = {387--407},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2014.02.004},
doi = {10.1016/J.VLSI.2014.02.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/MichailATG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/MorgenshteinYKF14,
author = {Arkadiy Morgenshtein and
Viacheslav Yuzhaninov and
Alexey Kovshilovsky and
Alexander Fish},
title = {Full-Swing Gate Diffusion Input logic - Case-study of low-power {CLA}
adder design},
journal = {Integr.},
volume = {47},
number = {1},
pages = {62--70},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.04.002},
doi = {10.1016/J.VLSI.2013.04.002},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/MorgenshteinYKF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/OkobiahMK14,
author = {Oghenekarho Okobiah and
Saraju P. Mohanty and
Elias Kougianos},
title = {Nano-CMOS thermal sensor design optimization for efficient temperature
measurement},
journal = {Integr.},
volume = {47},
number = {2},
pages = {195--203},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.001},
doi = {10.1016/J.VLSI.2013.10.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/OkobiahMK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkCHS14,
author = {Sun{-}Mi Park and
Ku{-}Young Chang and
Dowon Hong and
Changho Seo},
title = {New efficient bit-parallel polynomial basis multiplier for special
pentanomials},
journal = {Integr.},
volume = {47},
number = {1},
pages = {130--139},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.03.001},
doi = {10.1016/J.VLSI.2013.03.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkCHS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ParkK14,
author = {Sangdo Park and
Taewhan Kim},
title = {Edge layer embedding algorithm for mitigating on-package variation
in 3D clock tree synthesis},
journal = {Integr.},
volume = {47},
number = {4},
pages = {476--486},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.12.005},
doi = {10.1016/J.VLSI.2013.12.005},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ParkK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/RihoN14,
author = {Yoshiro Riho and
Kazuo Nakazato},
title = {A new extension method of retention time for memory cell on dynamic
random access memory},
journal = {Integr.},
volume = {47},
number = {3},
pages = {329--338},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.004},
doi = {10.1016/J.VLSI.2013.10.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/RihoN14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SantosHG14,
author = {Mauro Santos and
Nuno Horta and
Jorge Guilherme},
title = {A survey on nonlinear analog-to-digital converters},
journal = {Integr.},
volume = {47},
number = {1},
pages = {12--22},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.06.001},
doi = {10.1016/J.VLSI.2013.06.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SantosHG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SerafySS14,
author = {Caleb Serafy and
Bing Shi and
Ankur Srivastava},
title = {A geometric approach to chip-scale {TSV} shield placement for the
reduction of {TSV} coupling in 3D-ICs},
journal = {Integr.},
volume = {47},
number = {3},
pages = {307--317},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.004},
doi = {10.1016/J.VLSI.2013.11.004},
timestamp = {Wed, 05 Feb 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SerafySS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ShaphirPW14,
author = {Eugene Shaphir and
Ron Y. Pinter and
Shmuel Wimer},
title = {Cell-based interconnect migration by hierarchical optimization},
journal = {Integr.},
volume = {47},
number = {2},
pages = {161--174},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.003},
doi = {10.1016/J.VLSI.2013.10.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ShaphirPW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SitikT14,
author = {Can Sitik and
Baris Taskin},
title = {Iterative skew minimization for low swing clocks},
journal = {Integr.},
volume = {47},
number = {3},
pages = {356--364},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.007},
doi = {10.1016/J.VLSI.2013.10.007},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SitikT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SivananthamPGMP14,
author = {S. Sivanantham and
M. Padmavathy and
Ganga Gopakumar and
Partha Sharathi Mallick and
J. Raja Paul Perinbam},
title = {Enhancement of test data compression with multistage encoding},
journal = {Integr.},
volume = {47},
number = {4},
pages = {499--509},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.12.001},
doi = {10.1016/J.VLSI.2013.12.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SivananthamPGMP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VerbitskyDGB14,
author = {Dmitry Verbitsky and
Rostislav (Reuven) Dobkin and
Ran Ginosar and
Salomon Beer},
title = {StarSync: An extendable standard-cell mesochronous synchronizer},
journal = {Integr.},
volume = {47},
number = {2},
pages = {250--260},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.09.003},
doi = {10.1016/J.VLSI.2013.09.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/VerbitskyDGB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VijaykumarE14,
author = {V. R. Vijaykumar and
Elango Sekar},
title = {Hardware implementation of tag-reader mutual authentication protocol
for {RFID} systems},
journal = {Integr.},
volume = {47},
number = {1},
pages = {123--129},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.03.002},
doi = {10.1016/J.VLSI.2013.03.002},
timestamp = {Wed, 09 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/VijaykumarE14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WangAS14,
author = {Hailang Wang and
Mohammad H. Asgari and
Emre Salman},
title = {Compact model to efficiently characterize TSV-to-transistor noise
coupling in 3D ICs},
journal = {Integr.},
volume = {47},
number = {3},
pages = {296--306},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.10.006},
doi = {10.1016/J.VLSI.2013.10.006},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WangAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WeyS14,
author = {I{-}Chyn Wey and
Ye{-}Jhih Shen},
title = {Hardware-efficient common-feedback Markov-random-field probabilistic-based
noise-tolerant {VLSI} circuits},
journal = {Integr.},
volume = {47},
number = {4},
pages = {431--442},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.12.003},
doi = {10.1016/J.VLSI.2013.12.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WeyS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/WilleSMD14,
author = {Robert Wille and
Mathias Soeken and
D. Michael Miller and
Rolf Drechsler},
title = {Trading off circuit lines and gate costs in the synthesis of reversible
logic},
journal = {Integr.},
volume = {47},
number = {2},
pages = {284--294},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.08.002},
doi = {10.1016/J.VLSI.2013.08.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/WilleSMD14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Wimer14,
author = {Shmuel Wimer},
title = {Planar {CMOS} to multi-gate layout conversion for maximal fin utilization},
journal = {Integr.},
volume = {47},
number = {1},
pages = {115--122},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.03.004},
doi = {10.1016/J.VLSI.2013.03.004},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/Wimer14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/XieWP14,
author = {Qing Xie and
Yanzhi Wang and
Massoud Pedram},
title = {Designing soft-edge flip-flop-based linear pipelines operating in
multiple supply voltage regimes},
journal = {Integr.},
volume = {47},
number = {3},
pages = {318--328},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.11.003},
doi = {10.1016/J.VLSI.2013.11.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/XieWP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/Yan14,
author = {Jin{-}Tai Yan},
title = {Fault-tolerant analysis of {TMR} design with noise-aware logic},
journal = {Integr.},
volume = {47},
number = {4},
pages = {452--460},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2014.02.002},
doi = {10.1016/J.VLSI.2014.02.002},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/Yan14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ZhaoYCSC14,
author = {Wei Zhao and
Hailong Yao and
Yici Cai and
Subarna Sinha and
Charles C. Chiang},
title = {Fast and scalable parallel layout decomposition in double patterning
lithography},
journal = {Integr.},
volume = {47},
number = {2},
pages = {175--183},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.09.002},
doi = {10.1016/J.VLSI.2013.09.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ZhaoYCSC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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